[coreboot-gerrit] New patch to review for coreboot: 4f0e61e Family14: Add support for solder-down DDR memory

[Dave Frodin (dave.frodin@se-eng.com)]

Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4532

-gerrit

commit 4f0e61eabe3d03662687f53d9167dd9c790f7e5c
Author: Dave Frodin <dave.frodin at se-eng.com>
Date:   Wed Dec 11 13:28:25 2013 -0700

    Family14: Add support for solder-down DDR memory
    
    Normally the memory configuration/settings would be
    read from a DIMM/SODIMMs SPD. This change adds support
    for solder-down memory that doesn't have a SPD. The
    data that would normally be read from the SPD instead
    comes from a file.
    
    Change-Id: Ic10b0c5ca16cbc6af9400ef706392adcb151ac97
    Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
 src/northbridge/amd/agesa/Kconfig            |  9 ++++
 src/northbridge/amd/agesa/family14/dimmSpd.c | 75 ++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)

diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index d5c039f..f9a2d70 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2013 Sage Electronic Engineering, LLC
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -31,6 +32,14 @@ config S3_VGA_ROM_RUN
 	bool
 	default n
 
+config DDR3_SOLDERED_DOWN
+	bool
+	default n
+
+config PATH_TO_DDR3_SPD
+	string
+	default ""
+
 source src/northbridge/amd/agesa/family10/Kconfig
 source src/northbridge/amd/agesa/family12/Kconfig
 source src/northbridge/amd/agesa/family14/Kconfig
diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c
index a3f5bb3..c54e269 100644
--- a/src/northbridge/amd/agesa/family14/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family14/dimmSpd.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,9 +30,15 @@
 #include "dimmSpd.h"
 #include "chip.h"
 
+#if CONFIG_DDR3_SOLDERED_DOWN
+#include CONFIG_PATH_TO_DDR3_SPD
+AGESA_STATUS calc_fake_spd_crc( UINT8 *SPDPtr, UINT16 *crc );
+#endif
+
 /* uncomment for source level debug - GDB gets really confused otherwise. */
 //#pragma optimize ("", off)
 
+#if !CONFIG_DDR3_SOLDERED_DOWN
 /**
  *	Read a single SPD byte.  If the first byte is being read, set up the
  *	address and offset. Following bytes auto increment.
@@ -143,3 +150,71 @@ AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr)
 		return AGESA_ERROR;
 	return readspd(SMBUS0_BASE_ADDRESS, spdAddress, (void *)info->Buffer, 128);
 }
+
+#else // CONFIG_DDR3_SOLDERED_DOWN
+/*
+ * Get the SPD from the mainboard
+ */
+AGESA_STATUS agesa_ReadSPD(UINT32 unused1, UINT32 unused2, void *infoptr)
+{
+	UINT8 *spd_ptr;
+	UINT16 index, crc;
+
+	AGESA_READ_SPD_PARAMS *info = infoptr;
+	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+
+	if ((dev == 0) || (dev->chip_info == 0))
+		return AGESA_ERROR;
+
+	if (info->MemChannelId > CONFIG_DDR3_CHANNEL_MAX) return AGESA_ERROR;
+	if (info->SocketId     != 0)  return AGESA_ERROR;
+	if (info->DimmId       != 0)  return AGESA_ERROR;
+
+	/* read the bytes from the table */
+	spd_ptr = (UINT8 *)info->Buffer;
+	for (index = 0; index < 128; index++)
+		spd_ptr[index] = ddr3_fake_spd[index];
+
+	/* If CRC bytes are zeroes, calculate and store the CRC of the fake table */
+	if ((spd_ptr[126] == 0) && (spd_ptr[127] == 0)) {
+		calc_fake_spd_crc( spd_ptr, &crc );
+		spd_ptr[126] = (UINT8)(crc & 0xFF);
+		spd_ptr[127] = (UINT8)(crc>>8);
+	}
+
+	/* print out the table */
+	printk(BIOS_SPEW, "\nDump the fake SPD for Channel %d\n",info->MemChannelId);
+	for (index = 0; index < 128; index++) {
+		if((index&0x0F)==0x00) printk(BIOS_SPEW, "%02x:  ",index);
+		printk(BIOS_SPEW, "%02x ", spd_ptr[index]);
+		if((index&0x0F)==0x0F) printk(BIOS_SPEW, "\n");
+	}
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS calc_fake_spd_crc( UINT8 *SPDPtr, UINT16 *crc )
+{
+	INT16 i;
+	INT16 j;
+	INT16 jmax;
+
+	/* should the CRC be done on bytes 0-116 or 0-125 ? */
+	if (SPDPtr[0] & 0x80)
+		 jmax = 117;
+	else jmax = 126;
+
+	*crc = 0; /* zero out the CRC */
+
+	for (j = 0; j < jmax; j++) {
+		*crc = *crc ^ ((UINT16)SPDPtr[j] << 8);
+		for (i = 0; i < 8; i++) {
+			if (*crc & 0x8000) {
+				*crc = (*crc << 1) ^ 0x1021;
+			} else {
+				*crc = (*crc << 1);
+			}
+		}
+	}
+	return TRUE;
+}
+#endif