[coreboot-gerrit] Patch set updated for coreboot: d6b4a37 peppy: Set optimal DTLE register values
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Fri Dec 20 23:32:25 CET 2013
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4476
-gerrit
commit d6b4a37c7522f8108d3f7d255d64ecedec970228
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date: Tue Aug 13 10:50:15 2013 -0700
peppy: Set optimal DTLE register values
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA /
EDGE on Peppy.
Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9
Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65717
Reviewed-by: Marc Jones <marc.jones at se-eng.com>
---
src/mainboard/google/peppy/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb
index 06ca93c..b19f04b 100644
--- a/src/mainboard/google/peppy/devicetree.cb
+++ b/src/mainboard/google/peppy/devicetree.cb
@@ -70,6 +70,10 @@ chip northbridge/intel/haswell
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ # DTLE DATA / EDGE values
+ register "sata_port0_gen3_dtle" = "0x5"
+ register "sata_port1_gen3_dtle" = "0x5"
+
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V
register "sio_i2c1_voltage" = "0" # 3.3V
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