[coreboot-gerrit] Patch set updated for coreboot: 4f673c0 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Fri Dec 20 23:32:54 CET 2013


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4423

-gerrit

commit 4f673c0ce0f16b5795defaca9910cff87c832f5f
Author: Furquan Shaikh <furquan at google.com>
Date:   Thu Aug 1 13:58:17 2013 -0700

    Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
    
    Depending upon the values decoded from edid, the function decides the appropriate bits to
    be set in flags parameter (Important for fastboot to work correctly in kernel)
    
    Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856
    Reviewed-on: https://gerrit.chromium.org/gerrit/64265
    Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
    Commit-Queue: Furquan Shaikh <furquan at chromium.org>
    Tested-by: Furquan Shaikh <furquan at chromium.org>
---
 src/drivers/intel/gma/i915.h      |  4 +++-
 src/drivers/intel/gma/intel_ddi.c | 10 ++++++++--
 src/mainboard/google/slippy/gma.c |  4 +++-
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 12a7ee0..9a6314e 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -228,7 +228,9 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
 				    enum pipe pipe,
 				    int type,
 				    int lane_count,
-				    int pf_sz);
+				    int pf_sz,
+				    u8 phsync,
+				    u8 pvsync);
 
 enum transcoder intel_ddi_get_transcoder(enum port port,
 					 enum pipe pipe);
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index ff8ad4c..9ddd781 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -163,7 +163,9 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
 				    enum pipe pipe,
 				    int type,
 				    int lane_count,
-				    int pf_sz)
+				    int pf_sz,
+				    u8 phsync,
+				    u8 pvsync)
 {
 	u32 temp;
 
@@ -206,7 +208,11 @@ u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
 		}
 	}
 
-	/* We need to check for TRANS_DDI_PVSYNC and TRANS_DDI_PHSYNC -- How? */
+	if (phsync)
+		temp |= TRANS_DDI_PHSYNC;
+
+	if (pvsync)
+		temp |= TRANS_DDI_PVSYNC;
 
 	if (type == INTEL_OUTPUT_HDMI) {
 		/* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 026bba1..1d79d78 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -293,7 +293,9 @@ void dp_init_dim_regs(struct intel_dp *dp)
 						    dp->pipe,
 						    dp->type,
 						    dp->lane_count,
-						    dp->pfa_sz);
+						    dp->pfa_sz,
+						    dp->edid.phsync == '+'?1:0,
+						    dp->edid.pvsync == '+'?1:0);
 
 	dp->transcoder = intel_ddi_get_transcoder(dp->port,
 						  dp->pipe);



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