[coreboot-gerrit] New patch to review for coreboot: 3219780 src/vendorcode/amd/: punctuation cleanup [2/2].

[Idwer Vollering (vidwer@gmail.com)]

Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4564

-gerrit

commit 3219780c5b569982d390a8b8ef3d1f5c772b9eb2
Author: Idwer Vollering <vidwer at gmail.com>
Date:   Sun Dec 22 21:38:18 2013 +0000

    src/vendorcode/amd/: punctuation cleanup [2/2].
    
    Clean up superfluous line terminators.
    
    Change-Id: I3b0a77d971e9cd3cfd4413680841623051f4286c
    Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
 src/southbridge/amd/sb800/early_setup.c                                 | 2 +-
 .../agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c  | 2 +-
 .../agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c  | 2 +-
 src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c                             | 2 +-
 src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c                             | 2 +-
 src/vendorcode/amd/cimx/sb800/DISPATCHER.c                              | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index b3d16bf..213cae9 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -276,7 +276,7 @@ void sb800_pci_port80(void)
 	pci_write_config8(dev, 0x04, byte);
 
 	/* LPC controller */
-	dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+	dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
 
 	byte = pci_read_config8(dev, 0x4A);
 	byte &= ~(1 << 5);	/* disable lpc port 80 */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index 370a825..ab86118 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -533,7 +533,7 @@ PcieTopologyInitSrbmReset (
   )
 {
   UINT32 pcireg;
-  UINT32 regmask = 0x7030;;
+  UINT32 regmask = 0x7030;
   pcireg = PcieRegisterRead (
                                Wrapper,
                                WRAP_SPACE (Wrapper->WrapId, 0x8063),
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
index ae9fd5c..fa48682 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -531,7 +531,7 @@ PcieTopologyInitSrbmReset (
   )
 {
   UINT32 pcireg;
-  UINT32 regmask = 0x7030;;
+  UINT32 regmask = 0x7030;
   pcireg = PcieRegisterRead (
                                Wrapper,
                                WRAP_SPACE (Wrapper->WrapId, 0x8063),
diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
index 55adc8a..61bc58c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
@@ -837,7 +837,7 @@ LibAmdPciWrite (
       LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
     }
     //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
-    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
     //printk(BIOS_DEBUG, "LibAmdPciWrite\n");
   } else {
     // Setup the MMIO address
diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
index 99a28b1..d0e66b9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
@@ -842,7 +842,7 @@ LibAmdPciWrite (
       LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
     }
     //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
-    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
+    //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
     //printk(BIOS_DEBUG, "LibAmdPciWrite\n");
   } else {
     // Setup the MMIO address
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
index 3a8b32f..9a64e7e 100644
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
@@ -159,7 +159,7 @@ AmdSbDispatcher (
   }
 
   if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
-    sbECfancontrolservice((AMDSBCFG*)pConfig);;
+    sbECfancontrolservice((AMDSBCFG*)pConfig);
   }
 #endif
   return Status;