[coreboot-gerrit] New patch to review for coreboot: bbfc6e9 Remove dead files from Super I/O dir

Alec Ari (neotheuser@ymail.com) gerrit at coreboot.org
Mon Dec 30 08:37:42 CET 2013


Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4590

-gerrit

commit bbfc6e98c10c3fb94a933bfeb11f70e4dc783ee7
Author: Alec Ari <neotheuser at ymail.com>
Date:   Mon Dec 30 01:28:14 2013 -0600

    Remove dead files from Super I/O dir
    
    early_serial (or early_init) are only used by
    the following chips:
    
    Nuvoton WPCM450
    ITE IT8728F
    SMSC SIO1007
    Winbond W83627DHG
    
    This patch only removes files that are not in use
    and does not destroy support for any motherboards.
    
    This threw me off a bit when adding support for
    Nuvoton NCT6779D
    
    Change-Id: Ieaa96fb51647328350fae827832eef745ee75bce
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/superio/Kconfig                            |   1 -
 src/superio/Makefile.inc                       |   1 -
 src/superio/fintek/f71805f/early_serial.c      |  47 ---------
 src/superio/fintek/f71859/early_serial.c       |  47 ---------
 src/superio/fintek/f71863fg/early_serial.c     |  47 ---------
 src/superio/fintek/f71872/early_serial.c       |  47 ---------
 src/superio/fintek/f71889/early_serial.c       |  46 ---------
 src/superio/intel/i3100/early_serial.c         |  56 -----------
 src/superio/ite/it8661f/early_serial.c         |  79 ---------------
 src/superio/ite/it8671f/early_serial.c         | 105 --------------------
 src/superio/ite/it8673f/early_serial.c         |  90 -----------------
 src/superio/ite/it8705f/early_serial.c         |  82 ----------------
 src/superio/ite/it8712f/early_serial.c         | 117 ----------------------
 src/superio/ite/it8716f/early_init.c           |  37 -------
 src/superio/ite/it8716f/early_serial.c         |  62 ------------
 src/superio/ite/it8718f/early_serial.c         | 104 --------------------
 src/superio/ite/it8721f/early_serial.c         |  93 ------------------
 src/superio/ite/it8772f/early_serial.c         | 131 -------------------------
 src/superio/nsc/pc8374/early_init.c            |  56 -----------
 src/superio/nsc/pc87309/early_serial.c         |  30 ------
 src/superio/nsc/pc87351/early_serial.c         |  31 ------
 src/superio/nsc/pc87360/early_serial.c         |  31 ------
 src/superio/nsc/pc87366/early_serial.c         |  31 ------
 src/superio/nsc/pc87392/early_serial.c         |  30 ------
 src/superio/nsc/pc87417/early_init.c           |  54 ----------
 src/superio/nsc/pc87417/early_serial.c         |  38 -------
 src/superio/nsc/pc87427/early_init.c           |  54 ----------
 src/superio/nsc/pc97317/early_serial.c         |  49 ---------
 src/superio/nuvoton/nct5104d/Makefile.inc      |   1 -
 src/superio/nuvoton/nct5104d/early_init.c      |  47 ---------
 src/superio/serverengines/Kconfig              |  21 ----
 src/superio/serverengines/pilot/early_init.c   | 122 -----------------------
 src/superio/serverengines/pilot/early_serial.c |  57 -----------
 src/superio/serverengines/pilot/pilot.h        |  33 -------
 src/superio/smsc/fdc37m60x/early_serial.c      |  77 ---------------
 src/superio/smsc/lpc47b272/early_serial.c      |  53 ----------
 src/superio/smsc/lpc47b397/early_serial.c      |  46 ---------
 src/superio/smsc/lpc47m10x/early_serial.c      |  51 ----------
 src/superio/smsc/lpc47m15x/early_serial.c      |  45 ---------
 src/superio/smsc/lpc47n207/early_serial.c      |  97 ------------------
 src/superio/smsc/lpc47n217/early_serial.c      | 123 -----------------------
 src/superio/smsc/lpc47n227/early_serial.c      | 125 -----------------------
 src/superio/smsc/smscsuperio/early_serial.c    |  46 ---------
 src/superio/winbond/w83627ehg/early_init.c     |  38 -------
 src/superio/winbond/w83627ehg/early_serial.c   |  46 ---------
 src/superio/winbond/w83627hf/early_init.c      |  38 -------
 src/superio/winbond/w83627hf/early_serial.c    |  59 -----------
 src/superio/winbond/w83627thg/early_serial.c   |  58 -----------
 src/superio/winbond/w83627uhg/early_serial.c   |  57 -----------
 src/superio/winbond/w83697hf/early_serial.c    |  56 -----------
 src/superio/winbond/w83977f/early_serial.c     |  45 ---------
 src/superio/winbond/w83977tf/early_serial.c    |  47 ---------
 52 files changed, 2984 deletions(-)

diff --git a/src/superio/Kconfig b/src/superio/Kconfig
index 32e60bb..2e84430 100644
--- a/src/superio/Kconfig
+++ b/src/superio/Kconfig
@@ -26,7 +26,6 @@ source src/superio/ite/Kconfig
 source src/superio/nsc/Kconfig
 source src/superio/nuvoton/Kconfig
 source src/superio/renesas/Kconfig
-source src/superio/serverengines/Kconfig
 source src/superio/smsc/Kconfig
 source src/superio/via/Kconfig
 source src/superio/winbond/Kconfig
diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc
index e34fa89..a8f9d49 100644
--- a/src/superio/Makefile.inc
+++ b/src/superio/Makefile.inc
@@ -23,7 +23,6 @@ subdirs-y += ite
 subdirs-y += nsc
 subdirs-y += nuvoton
 subdirs-y += renesas
-#subdirs-y += serverengines
 subdirs-y += smsc
 subdirs-y += via
 subdirs-y += winbond
diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c
deleted file mode 100644
index 827f870..0000000
--- a/src/superio/fintek/f71805f/early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */
-
-#include <arch/io.h>
-#include "f71805f.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void f71805f_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c
deleted file mode 100644
index 4401714..0000000
--- a/src/superio/fintek/f71859/early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Jones <marcj303 at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */
-
-#include <arch/io.h>
-#include "f71859.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void f71859_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c
deleted file mode 100644
index 5d1cfb7..0000000
--- a/src/superio/fintek/f71863fg/early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */
-
-#include <arch/io.h>
-#include "f71863fg.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void f71863fg_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c
deleted file mode 100644
index af5cdb3..0000000
--- a/src/superio/fintek/f71872/early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey at slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */
-
-#include <arch/io.h>
-#include "f71872.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void f71872_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c
deleted file mode 100644
index 9623cbd..0000000
--- a/src/superio/fintek/f71889/early_serial.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Alec Ari <neotheuser at ymail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include "f71889.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void f71889_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c
deleted file mode 100644
index f95cf8a..0000000
--- a/src/superio/intel/i3100/early_serial.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "i3100.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	outb(0x80, port);
-	outb(0x86, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	outb(0x68, port);
-	outb(0x08, port);
-}
-
-/* Enable device interrupts, set UART_CLK predivide. */
-static void i3100_configure_uart_clk(device_t dev, u8 predivide)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1);
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void i3100_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c
deleted file mode 100644
index ee132fa..0000000
--- a/src/superio/ite/it8661f/early_serial.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8661f.h"
-
-/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
-/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
-/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
-/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	int i;
-	u16 port = dev >> 8;
-
-	/* TODO: Don't hardcode Super I/O config port to 0x3f0. */
-	outb(0x86, IT8661F_ISA_PNP_PORT);
-	outb(0x80, IT8661F_ISA_PNP_PORT);
-	outb(0x55, IT8661F_ISA_PNP_PORT);
-	outb(0x55, IT8661F_ISA_PNP_PORT);
-
-	/* Sequentially write the 32 special values. */
-	for (i = 0; i < 32; i++)
-		outb(init_values[i], port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	pnp_write_config(dev, IT8661F_REG_CC, (1 << 1));
-}
-
-/*
- * The logical devices will only be involved in the ISA PnP sequence if their
- * respective enable bits in IT8661F_REG_LDE are set.
- *
- * TODO: Find out if we actually need this (we use MB PnP mode).
- *
- * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
- */
-static void it8661f_enable_logical_devices(device_t dev)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void it8661f_set_clkin(device_t dev, u8 clkin)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void it8661f_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c
deleted file mode 100644
index c2ba6e0..0000000
--- a/src/superio/ite/it8671f/early_serial.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8671f.h"
-
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE                   0x3f0
-#define SIO_INDEX                  SIO_BASE
-#define SIO_DATA                   (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8671F_CONFIG_REG_CC      0x02   /* Configure Control (write-only). */
-#define IT8671F_CONFIG_REG_LDN     0x07   /* Logical Device Number. */
-#define IT8671F_CONFIG_REG_LDE     0x23   /* PnP Logical Device Enable. */
-#define IT8671F_CONFIG_REG_SWSUSP  0x24   /* Software Suspend. */
-
-#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
-
-/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
- */
-static const u8 init_values[] = {
-	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
-	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
-	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
-	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
-
-static void it8671f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-/* Enter the configuration state (MB PnP mode). */
-static void it8671f_enter_conf(void)
-{
-	int i;
-
-	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
-	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
-	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
-	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-	outb(0x86, IT8671F_CONFIGURATION_PORT);
-	outb(0x80, IT8671F_CONFIGURATION_PORT);
-	outb(0x55, IT8671F_CONFIGURATION_PORT);
-	outb(0x55, IT8671F_CONFIGURATION_PORT);
-
-	/* Sequentially write the 32 special values. */
-	for (i = 0; i < 32; i++)
-		outb(init_values[i], SIO_BASE);
-}
-
-/* Exit the configuration state (MB PnP mode). */
-static void it8671f_exit_conf(void)
-{
-	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 48MHz CLKIN (24MHz is the default). */
-void it8671f_48mhz_clkin(void)
-{
-	it8671f_enter_conf();
-	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
-	it8671f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-static void it8671f_enable_serial(device_t dev, u16 iobase)
-{
-	it8671f_enter_conf();
-
-	/*
-	 * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
-         * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7).
-	 */
-	it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
-
-	/* Enable serial port(s). */
-	it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
-	it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
-
-	it8671f_exit_conf();
-}
diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c
deleted file mode 100644
index 987b5e6..0000000
--- a/src/superio/ite/it8673f/early_serial.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8673f.h"
-
-/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
-#define SIO_BASE                    0x3f0
-#define SIO_INDEX                   SIO_BASE
-#define SIO_DATA                    (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8673F_CONFIG_REG_CC       0x02   /* Configure Control (write-only). */
-#define IT8673F_CONFIG_REG_LDN      0x07   /* Logical Device Number. */
-#define IT8673F_CONFIG_REG_CLOCKSEL 0x23   /* Clock Selection. */
-#define IT8673F_CONFIG_REG_SWSUSP   0x24   /* Software Suspend. */
-
-#define IT8673F_CONFIGURATION_PORT  0x0279 /* Write-only. */
-
-/*
- * Special values used for entering MB PnP mode. The first four bytes of
- * each line determine the address port, the last four are data.
- */
-static const u8 init_values[] = {
-	0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
-	0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
-	0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1,
-	0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
-};
-
-static void it8673f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8673F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-/* Enable the serial port(s). */
-static void it8673f_enable_serial(device_t dev, u16 iobase)
-{
-	int i;
-
-	/* (1) Enter the configuration state (MB PnP mode). */
-
-	/* Perform MB PnP setup to put the SIO chip at 0x3f0. */
-	/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
-	/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
-	/* Base address 0x370: 0x86 0x80 0xaa 0x55. */
-	outb(0x86, IT8673F_CONFIGURATION_PORT);
-	outb(0x80, IT8673F_CONFIGURATION_PORT);
-	outb(0x55, IT8673F_CONFIGURATION_PORT);
-	outb(0x55, IT8673F_CONFIGURATION_PORT);
-
-	/* Sequentially write the 32 special values. */
-	for (i = 0; i < 32; i++)
-		outb(init_values[i], SIO_BASE);
-
-	/* (2) Modify the data of configuration registers. */
-
-	/* Enable all devices. */
-	it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Select 24MHz CLKIN (clear bit 0). */
-	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00);
-
-	/* Clear software suspend mode (clear bit 0). */
-	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00);
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02);
-}
diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c
deleted file mode 100644
index ccc92c2..0000000
--- a/src/superio/ite/it8705f/early_serial.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8705f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     0x2e
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8705F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8705F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-
-/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */
-#define IT8705F_CONFIG_REG_CLOCKSEL  0x24 /* Clock Selection, Flash I/F. */
-#define IT8705F_CONFIG_REG_SWSUSP    0x23 /* Software Suspend. */
-
-#define IT8705F_CONFIGURATION_PORT   0x2e /* Write-only. */
-
-static void it8705f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8705F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-/* Enable the serial port(s). */
-static void it8705f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-
-	/* Perform MB PnP setup to put the SIO chip at 0x2e. */
-	/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
-	/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
-	outb(0x87, IT8705F_CONFIGURATION_PORT);
-	outb(0x01, IT8705F_CONFIGURATION_PORT);
-	outb(0x55, IT8705F_CONFIGURATION_PORT);
-	outb(0x55, IT8705F_CONFIGURATION_PORT);
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Select 24MHz CLKIN (set bit 0). */
-	it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01);
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02);
-}
diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c
deleted file mode 100644
index 51564fc..0000000
--- a/src/superio/ite/it8712f/early_serial.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8712f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     0x2e
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8712F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8712F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8712F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8712F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
-#define IT8712F_CONFIG_REG_MFC       0x2a /* Multi-function control */
-#define IT8712F_CONFIG_REG_WATCHDOG  0x72 /* Watchdog control. */
-
-static void it8712f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-static void it8712f_enter_conf(void)
-{
-	u16 port = 0x2e; /* TODO: Don't hardcode! */
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8712f_exit_conf(void)
-{
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz is the default). */
-void it8712f_24mhz_clkin(void)
-{
-	it8712f_enter_conf();
-	it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8712f_exit_conf();
-}
-
-/*
- * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2!
- *
- * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
- *
- * Enable 3VSBSW#. (For System Suspend-to-RAM)
- * 0: 3VSBSW# will be always inactive.
- * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
- */
-void it8712f_enable_3vsbsw(void)
-{
-	it8712f_enter_conf();
-	it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80);
-	it8712f_exit_conf();
-}
-
-void it8712f_kill_watchdog(void)
-{
-	it8712f_enter_conf();
-	it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
-	it8712f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8712f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8712f_enter_conf();
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-
-	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8712f_exit_conf();
-}
diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c
deleted file mode 100644
index cfac2a9..0000000
--- a/src/superio/ite/it8716f/early_init.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8716f.h"
-
-void it8716f_disable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-}
-
-void it8716f_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c
deleted file mode 100644
index 02f0304..0000000
--- a/src/superio/ite/it8716f/early_serial.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8716f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     0x2e
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8716F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8716F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8716F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8716F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02);
-}
-
-void it8716f_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c
deleted file mode 100644
index 308b67c..0000000
--- a/src/superio/ite/it8718f/early_serial.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8718f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     0x2e
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8718F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8718F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
-#define IT8718F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8718F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
-
-static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-static void it8718f_enter_conf(void)
-{
-	u16 port = 0x2e; /* TODO: Don't hardcode! */
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8718f_exit_conf(void)
-{
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz default). */
-void it8718f_24mhz_clkin(void)
-{
-	it8718f_enter_conf();
-	it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8718f_exit_conf();
-}
-
-/*
- * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
- * mechanism. It lives in the GPIO LDN. However, register 0xEF is not
- * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
- */
-void it8718f_disable_reboot(void)
-{
-	it8718f_enter_conf();
-	it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
-	it8718f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8718f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8718f_enter_conf();
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8718f_exit_conf();
-}
diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c
deleted file mode 100644
index 20e19b6..0000000
--- a/src/superio/ite/it8721f/early_serial.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- * Copyright (C) 2011 QingPei Wang <wangqingpei at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "it8721f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     0x2e
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8721F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8721F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8721F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8721F_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
-
-static void it8721f_sio_write(u8 ldn, u8 index, u8 value)
-{
-	outb(IT8721F_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-static void it8721f_enter_conf(void)
-{
-	u16 port = 0x2e; /* TODO: Don't hardcode! */
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8721f_exit_conf(void)
-{
-	it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz default). */
-void it8721f_24mhz_clkin(void)
-{
-	it8721f_enter_conf();
-	it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8721f_exit_conf();
-}
-
-
-/* Enable the serial port(s). */
-void it8721f_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state (MB PnP mode). */
-	it8721f_enter_conf();
-
-	/* (2) Modify the data of configuration registers. */
-
-	/*
-	 * Select the chip to configure (if there's more than one).
-	 * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
-	 * If this register is not written, both chips are configured.
-	 */
-
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
-
-	/* Enable serial port(s). */
-	it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */
-	it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */
-
-	/* Clear software suspend mode (clear bit 0). TODO: Needed? */
-	/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
-
-	/* (3) Exit the configuration state (MB PnP mode). */
-	it8721f_exit_conf();
-}
diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c
deleted file mode 100644
index 8bf2964..0000000
--- a/src/superio/ite/it8772f/early_serial.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include "it8772f.h"
-
-/* The base address is 0x2e or 0x4e, depending on config bytes. */
-#define SIO_BASE                     IT8772F_BASE
-#define SIO_INDEX                    SIO_BASE
-#define SIO_DATA                     (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define IT8772F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
-#define IT8772F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
-#define IT8772F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
-#define IT8772F_CONFIG_REG_MFC       0x2a /* Multi-function control */
-#define IT8772F_CONFIG_REG_WATCHDOG  0x72 /* Watchdog control. */
-
-u8 it8772f_sio_read(u8 index)
-{
-	outb(index, SIO_BASE);
-	return inb(SIO_DATA);
-}
-
-void it8772f_sio_write(u8 index, u8 value)
-{
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-static void it8772f_enter_conf(void)
-{
-	u16 port = SIO_BASE;
-
-	outb(0x87, port);
-	outb(0x01, port);
-	outb(0x55, port);
-	outb((port == 0x4e) ? 0xaa : 0x55, port);
-}
-
-static void it8772f_exit_conf(void)
-{
-	it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
-}
-
-/* Select 24MHz CLKIN (48MHz is the default). */
-void it8772f_24mhz_clkin(void)
-{
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00);
-	it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1);
-	it8772f_exit_conf();
-}
-
-/*
- * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
- *
- * Enable 3VSBSW#. (For System Suspend-to-RAM)
- * 0: 3VSBSW# will be always inactive.
- * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
- */
-void it8772f_enable_3vsbsw(void)
-{
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
-	it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80);
-	it8772f_exit_conf();
-}
-
-void it8772f_kill_watchdog(void)
-{
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
-	it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00);
-	it8772f_exit_conf();
-}
-
-/* Enable the serial port(s). */
-void it8772f_enable_serial(device_t dev, u16 iobase)
-{
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff);
-	it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff);
-	it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff);
-	it8772f_sio_write(PNP_IDX_EN, 1);
-	it8772f_exit_conf();
-}
-
-/* Set AC resume to be up to the Southbridge */
-void it8772f_ac_resume_southbridge(void)
-{
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
-	it8772f_sio_write(0xf4, 0x60);
-	it8772f_exit_conf();
-}
-
-/* Configure a set of GPIOs */
-void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
-			u8 output, u8 enable)
-{
-	set--; /* Set 1 is offset 0 */
-	it8772f_enter_conf();
-	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
-	if (set < 5) {
-		it8772f_sio_write(GPIO_REG_SELECT(set), select);
-		it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
-		it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
-	}
-	it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
-	it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
-	it8772f_exit_conf();
-}
diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c
deleted file mode 100644
index d3f601d..0000000
--- a/src/superio/nsc/pc8374/early_init.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc8374.h"
-
-static void pc8374_enable(u16 iobase, u8 *init)
-{
-	u8 val, count;
-
-	outb(0x29, iobase);
-	val = inb(iobase + 1);
-	val |= 0x91;
-	outb(val, iobase + 1);
-
-	for (count = 0; count < 255; count++)
-		if (inb(iobase + 1) == 0x91)
-			break;
-
-	for (; *init; init++) {
-		outb(*init, iobase);
-		val = inb(iobase + 1);
-		init++;
-		val &= *init;
-		init++;
-		val |= *init;
-		outb(val, iobase + 1);
-	}
-}
-
-static void pc8374_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	if (iobase)
-		pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c
deleted file mode 100644
index 131f0aa..0000000
--- a/src/superio/nsc/pc87309/early_serial.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87309.h"
-
-static void pc87309_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c
deleted file mode 100644
index c34538f..0000000
--- a/src/superio/nsc/pc87351/early_serial.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87351.h"
-
-static void pc87351_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c
deleted file mode 100644
index da4abdb..0000000
--- a/src/superio/nsc/pc87360/early_serial.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87360.h"
-
-static void pc87360_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c
deleted file mode 100644
index e173afd..0000000
--- a/src/superio/nsc/pc87366/early_serial.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87366.h"
-
-static void pc87366_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c
deleted file mode 100644
index 6e85fb9..0000000
--- a/src/superio/nsc/pc87392/early_serial.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87392.h"
-
-static void pc87392_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c
deleted file mode 100644
index d1870f9..0000000
--- a/src/superio/nsc/pc87417/early_init.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87417.h"
-
-static void pc87417_disable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-}
-
-static void pc87417_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
-
-static void xbus_cfg(device_t dev)
-{
-	u8 i, data;
-	u16 xbus_index;
-
-	pnp_set_logical_device(dev);
-	/* Select proper BIOS size (4MB). */
-	pnp_write_config(dev, PC87417_XMEMCNF2,
-			 (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
-	xbus_index = pnp_read_iobase(dev, 0x60);
-
-	/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
-	for (i = 0; i <= 0xf; i++)
-		outb((i << 4), xbus_index + PC87417_HAP0);
-}
diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c
deleted file mode 100644
index 33bae7e..0000000
--- a/src/superio/nsc/pc87417/early_serial.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87417.h"
-
-void pc87417_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
-
-void pc87417_enable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c
deleted file mode 100644
index 6df1b9f..0000000
--- a/src/superio/nsc/pc87427/early_init.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc87427.h"
-
-static void pc87427_disable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-}
-
-static void pc87427_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
-
-static void xbus_cfg(device_t dev)
-{
-	u8 i, data;
-	u16 xbus_index;
-
-	pnp_set_logical_device(dev);
-
-	/* Select proper BIOS size (4MB). */
-	pnp_write_config(dev, PC87427_XMEMCNF2,
-			 (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
-	xbus_index = pnp_read_iobase(dev, 0x60);
-
-	/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
-	for (i = 0; i <= 0xf; i++)
-		outb((i << 4), xbus_index + PC87427_HAP0);
-}
diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c
deleted file mode 100644
index 0c21561..0000000
--- a/src/superio/nsc/pc97317/early_serial.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "pc97317.h"
-
-#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
-#define PM_BASE 0xe8
-
-/* The PC97317 needs clocks to be set up before the serial port will operate. */
-static void pc97317_enable_serial(device_t dev, u16 iobase)
-{
-	/* Set base address of power management unit. */
-	pnp_set_logical_device(PM_DEV);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
-	pnp_set_enable(dev, 1);
-
-	/* Use on-chip clock multiplier. */
-	outb(0x03, PM_BASE);
-	outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
-
-	/* Wait for the clock to stabilise. */
-	while(!(inb(PM_BASE + 1) & 0x80))
-		;
-
-	/* Set the base address of the port. */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc
index b9345aa..9947f50 100644
--- a/src/superio/nuvoton/nct5104d/Makefile.inc
+++ b/src/superio/nuvoton/nct5104d/Makefile.inc
@@ -18,6 +18,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-romstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c
 ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c
 
diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c
deleted file mode 100644
index 9c0cf0f..0000000
--- a/src/superio/nuvoton/nct5104d/early_init.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pnp_def.h>
-#include "nct5104d.h"
-
-static void pnp_enter_extended_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87,port);
-	outb(0x87,port);
-}
-
-static void pnp_exit_extended_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa,port);
-}
-
-static void nct5104d_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_extended_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev,0);
-	pnp_set_iobase(dev,PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev,1);
-	pnp_exit_extended_mode(dev);
-}
diff --git a/src/superio/serverengines/Kconfig b/src/superio/serverengines/Kconfig
deleted file mode 100644
index 7c15067..0000000
--- a/src/superio/serverengines/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Ronald G. Minnich
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-config SUPERIO_SERVERENGINES_PILOT
-	bool
diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c
deleted file mode 100644
index 1993c9e..0000000
--- a/src/superio/serverengines/pilot/early_init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for Univ. Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* PILOT Super I/O is only based on LPC observation done on factory system. */
-
-#define BLUBB_DEV PNP_DEV(port, 0x04)
-
-/*
- * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to
- * be another serial (?), it is also deactivated on the HP machine.
- */
-static void pilot_early_init(device_t dev)
-{
-	u16 port = dev >> 8;
-
-	print_debug("Using port: ");
-	print_debug_hex16(port);
-	print_debug("\n");
-	pilot_disable_serial(PNP_DEV(port, 0x1));
-	print_debug("disable serial 1\n");
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x3));
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, 0x60, 0x0b00);
-	pnp_set_iobase(dev, 0x62, 0x0b80);
-	pnp_set_iobase(dev, 0x64, 0x0b84);
-	pnp_set_iobase(dev, 0x66, 0x0b86);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-
-/*
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x3));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x3), 0);
-	pnp_exit_ext_func_mode(dev);
-*/
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x4));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable( PNP_DEV(port, 0x4), 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x5));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x5), 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x6));
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
-	pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 1);
-	pnp_set_drq(dev, 0x71, 3);
-	pnp_set_enable(dev, 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0xe));
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x70);
-	pnp_set_iobase(dev, PNP_IDX_IO1, 0x72);
-	pnp_set_irq(dev, PNP_IDX_IRQ0, 8);
-	pnp_set_drq(dev, 0x71, 3);
-	pnp_set_enable(dev, 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x7));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x7), 0);
-	pnp_exit_ext_func_mode(dev);
-
-/*
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x8));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x8), 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x9));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x9), 0);
-	pnp_exit_ext_func_mode(dev);
-
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(PNP_DEV(port, 0x10));
-	pnp_exit_ext_func_mode(dev);
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_enable(PNP_DEV(port, 0x10), 0);
-	pnp_exit_ext_func_mode(dev);
-*/
-}
diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c
deleted file mode 100644
index 4112901..0000000
--- a/src/superio/serverengines/pilot/early_serial.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for Univ. Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* PILOT Super I/O is only based on LPC observation done on factory system. */
-
-#include <arch/io.h>
-#include "pilot.h"
-
-/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x5A, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xA5, port);
-}
-
-/* Serial config is a fairly standard procedure. */
-static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void __attribute__((unused)) pilot_disable_serial(device_t dev)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000);
-	pnp_set_enable(dev, 0);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h
deleted file mode 100644
index a5bddd3..0000000
--- a/src/superio/serverengines/pilot/pilot.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 University of Heidelberg
- * Written by Mondrian Nuessle <nuessle at uni-heidelberg.de> for Univ. Heidelberg
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H
-#define SUPERIO_SERVERENGINES_PILOT_PILOT_H
-
-/* PILOT Super I/O is only based on LPC observation done on factory system. */
-
-#define PILOT_LD1 0x01 /* Logical device 1 */
-#define PILOT_SP1 0x02 /* Com1 */
-#define PILOT_LD4 0x04 /* Logical device 4 */
-#define PILOT_LD5 0x05 /* Logical device 5 */
-#define PILOT_LD7 0x07 /* Logical device 7 */
-
-#endif
diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c
deleted file mode 100644
index 38cb0f8..0000000
--- a/src/superio/smsc/fdc37m60x/early_serial.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "fdc37m60x.h"
-
-/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
-#define SIO_BASE                       0x3f0
-#define SIO_INDEX                      SIO_BASE
-#define SIO_DATA                       (SIO_BASE + 1)
-
-/* Global configuration registers. */
-#define FDC37M60X_CONFIG_REG_CC        0x02  /* Configure Control. */
-#define FDC37M60X_CONFIG_REG_LDN       0x07  /* Logical Device Number. */
-#define FDC37M60X_CONFIG_POWER_CONTROL 0x22  /* Power Control. */
-#define FDC37M60X_CONFIG_POWER_MGMT    0x23  /* Intelligent Power Mgmt. */
-#define FDC37M60X_CONFIG_OSC           0x24  /* OSC. */
-
-#define FDC37M60X_CONFIGURATION_PORT   0x3f0 /* Write-only. */
-
-/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
-   LDN the register belongs to, before you can access the register. */
-static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value)
-{
-	outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
-	outb(ldn, SIO_DATA);
-	outb(index, SIO_BASE);
-	outb(value, SIO_DATA);
-}
-
-/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
-static void fdc37m60x_enable_serial(device_t dev, u16 iobase)
-{
-	/* (1) Enter the configuration state. */
-	outb(0x55, FDC37M60X_CONFIGURATION_PORT);
-
-	/* (2) Modify the data of configuration registers. */
-
-	/* Power on all devices by setting the respective bit.
-	   Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */
-	fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39);
-
-	/* Disable intelligent power management. */
-	fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00);
-
-	/* Turn on OSC, turn on BRG clock. */
-	fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04);
-
-	/* Configure serial port 1. */
-	fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03);
-	fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */
-	fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */
-	fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */
-
-	/* Enable serial port 1. */
-	fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01);
-
-	/* (3) Exit the configuration state. */
-	outb(0xaa, FDC37M60X_CONFIGURATION_PORT);
-}
diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c
deleted file mode 100644
index b2f0d1b..0000000
--- a/src/superio/smsc/lpc47b272/early_serial.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */
-
-#include <arch/io.h>
-#include "lpc47b272.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47b272_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c
deleted file mode 100644
index 31d515b..0000000
--- a/src/superio/smsc/lpc47b397/early_serial.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "lpc47b397.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void lpc47b397_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c
deleted file mode 100644
index fc6efb9..0000000
--- a/src/superio/smsc/lpc47m10x/early_serial.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301  USA
- */
-
-#include <arch/io.h>
-#include "lpc47m10x.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c
deleted file mode 100644
index 7d75bae..0000000
--- a/src/superio/smsc/lpc47m15x/early_serial.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
-
-#include <arch/io.h>
-#include "lpc47m15x.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_conf_state(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c
deleted file mode 100644
index e2ae49d..0000000
--- a/src/superio/smsc/lpc47n207/early_serial.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/*
- * This code tries to discover the SMSC LPC47N207 superio chip which can be
- * connected over an LPC dongle. The chip could be bootstrap mapped to one of
- * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e.
- *
- * Initializing the UART requires accesses to a few control registers. This
- * structure includes the register offset and the value to write (along with
- * the mask).
- */
-typedef struct {
-	u8 conf_reg;
-	u8 value;
-	u8 mask;
-} uart_conf;
-
-/* All regs/values to write to initialize the LPC47N207 UART */
-static const uart_conf uart_conf_data [] = {
-	{2, (1 << 3), (1 << 3)},    /* cr02, enable Primary UART power */
-	{0xc, (1 << 6), (1 << 6)},  /* cr0c, enable Primary UART high speed */
-	{0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff},  /* cr24, base addr */
-};
-
-void try_enabling_LPC47N207_uart(void)
-{
-	u8 reg_value;
-	const uart_conf* conf_item;
-	u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
-	u16 lpc_port;
-	int i, j;
-
-#define CONFIG_ENABLE    0x55
-#define CONFIG_DISABLE   0xaa
-
-	for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) {
-		lpc_port = lpc_ports[j];
-
-		/* enable CONFIG mode */
-		outb(CONFIG_ENABLE, lpc_port);
-		reg_value=inb(lpc_port);
-		if (reg_value != CONFIG_ENABLE) {
-			continue; /* There is no LPC device at this address */
-		}
-
-		do {
-			/*
-			 * Registers 12 and 13 hold config address, look for a
-			 * match.
-			 */
-			outb(0x12, lpc_port);
-			reg_value=inb(lpc_port + 1);
-			if (reg_value != (lpc_port & 0xff))
-			    break;
-
-			outb(0x13, lpc_port);
-			reg_value=inb(lpc_port + 1);
-			if (reg_value != (lpc_port >> 8))
-				break;
-
-			/* This must be the SMSC LPC 47N207, enable the UART. */
-			for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) {
-				u8 reg, value, mask;
-
-				conf_item = uart_conf_data + i;
-
-				reg = conf_item->conf_reg;
-				value = conf_item->value;
-				mask = conf_item->mask;
-
-				outb(reg, lpc_port);
-				reg_value = inb(lpc_port + 1);
-				reg_value &= ~mask;
-				reg_value |= (value & mask);
-				outb(reg_value, lpc_port + 1);
-			}
-		} while (0);
-		outb(CONFIG_DISABLE, lpc_port);
-	}
-}
diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c
deleted file mode 100644
index 451628a..0000000
--- a/src/superio/smsc/lpc47n217/early_serial.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */
-
-#include <arch/io.h>
-#include <assert.h>
-#include "lpc47n217.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-/**
- * Program the base I/O port for the specified logical device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Base I/O port for the logical device.
- */
-static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
-{
-	/* LPC47N217 requires base ports to be a multiple of 4. */
-	ASSERT(!(iobase & 0x3));
-
-	switch(dev & 0xFF) {
-	case LPC47N217_PP:
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-	case LPC47N217_SP1:
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-	case LPC47N217_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Enable or disable the specified logical device.
- *
- * Technically, a full disable requires setting the device's base I/O port
- * below 0x100. We don't do that here, because we don't have access to a data
- * structure that specifies what the 'real' base port is (when asked to enable
- * the device). Also the function is used only to disable the device while its
- * true base port is programmed (see lpc47n217_enable_serial() below).
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param enable 0 to disable, anythig else to enable.
- */
-static void lpc47n217_pnp_set_enable(device_t dev, int enable)
-{
-	u8 power_register = 0, power_mask = 0, current_power, new_power;
-
-	switch(dev & 0xFF) {
-	case LPC47N217_PP:
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-	case LPC47N217_SP1:
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-	case LPC47N217_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-	default:
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask; /* Disable by default. */
-	if (enable)
-		new_power |= power_mask;	 /* Enable. */
-	pnp_write_config(dev, power_register, new_power);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47n217_enable_serial(device_t dev, u16 iobase)
-{
-	/*
-	 * NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	 * support for logical devices, which the LPC47N217 doesn't have.
-	 */
-	pnp_enter_conf_state(dev);
-	lpc47n217_pnp_set_enable(dev, 0);
-	lpc47n217_pnp_set_iobase(dev, iobase);
-	lpc47n217_pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c
deleted file mode 100644
index 4aea7c5..0000000
--- a/src/superio/smsc/lpc47n227/early_serial.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */
-
-#include <arch/io.h>
-#include "lpc47n227.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x55, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-/**
- * Program the base I/O port for the specified logical device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Base I/O port for the logical device.
- */
-static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
-{
-	/* LPC47N227 requires base ports to be a multiple of 4. */
-	/* it's not very useful to do an ASSERT here: if it trips,
-	 * there's no console to report it.
-	ASSERT(!(iobase & 0x3));
-	*/
-
-	switch (dev & 0xFF) {
-	case LPC47N227_PP:
-		pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
-		break;
-	case LPC47N227_SP1:
-		pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
-		break;
-	case LPC47N227_SP2:
-		pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
-		break;
-	default:
-		break;
-	}
-}
-
-/**
- * Enable or disable the specified logical device.
- *
- * Technically, a full disable requires setting the device's base I/O port
- * below 0x100. We don't do that here, because we don't have access to a data
- * structure that specifies what the 'real' base port is (when asked to enable
- * the device). Also the function is used only to disable the device while its
- * true base port is programmed (see lpc47n227_enable_serial() below).
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param enable 0 to disable, anythig else to enable.
- */
-static void lpc47n227_pnp_set_enable(device_t dev, int enable)
-{
-	u8 power_register = 0, power_mask = 0, current_power, new_power;
-
-	switch (dev & 0xFF) {
-	case LPC47N227_PP:
-		power_register = 0x01;
-		power_mask = 0x04;
-		break;
-	case LPC47N227_SP1:
-		power_register = 0x02;
-		power_mask = 0x08;
-		break;
-	case LPC47N227_SP2:
-		power_register = 0x02;
-		power_mask = 0x80;
-		break;
-	default:
-		return;
-	}
-
-	current_power = pnp_read_config(dev, power_register);
-	new_power = current_power & ~power_mask; /* Disable by default. */
-	if (enable)
-		new_power |= power_mask; /* Enable. */
-	pnp_write_config(dev, power_register, new_power);
-}
-
-/**
- * Configure the base I/O port of the specified serial device and enable the
- * serial device.
- *
- * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
- * @param iobase Processor I/O port address to assign to this serial device.
- */
-static void lpc47n227_enable_serial(device_t dev, u16 iobase)
-{
-	/*
-	 * NOTE: Cannot use pnp_set_XXX() here because they assume chip
-	 * support for logical devices, which the LPC47N227 doesn't have.
-	 */
-	pnp_enter_conf_state(dev);
-	lpc47n227_pnp_set_enable(dev, 0);
-	lpc47n227_pnp_set_iobase(dev, iobase);
-	lpc47n227_pnp_set_enable(dev, 1);
-	pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c
deleted file mode 100644
index 5e9aadb..0000000
--- a/src/superio/smsc/smscsuperio/early_serial.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <device/pnp_def.h>
-
-/* All known/supported SMSC Super I/Os have the same logical device IDs
- * for the serial ports (COM1, COM2).
- */
-#define SMSCSUPERIO_SP1 4	/* Com1 */
-#define SMSCSUPERIO_SP2 5	/* Com2 */
-
-/**
- * Enable the specified serial port.
- *
- * @param dev The device to use.
- * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
- */
-static inline void smscsuperio_enable_serial(device_t dev, u16 iobase)
-{
-	u16 port = dev >> 8;
-
-	outb(0x55, port);		/* Enter the configuration state. */
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	outb(0xaa, port);		/* Exit the configuration state. */
-}
diff --git a/src/superio/winbond/w83627ehg/early_init.c b/src/superio/winbond/w83627ehg/early_init.c
deleted file mode 100644
index 7be5e37..0000000
--- a/src/superio/winbond/w83627ehg/early_init.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include "w83627ehg.h"
-
-void w83627ehg_disable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-}
-
-void w83627ehg_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c
deleted file mode 100644
index 1a895c6..0000000
--- a/src/superio/winbond/w83627ehg/early_serial.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627ehg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-void w83627ehg_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c
deleted file mode 100644
index 66b4098..0000000
--- a/src/superio/winbond/w83627hf/early_init.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627hf.h"
-
-void w83627hf_disable_dev(device_t dev)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-}
-
-void w83627hf_enable_dev(device_t dev, u16 iobase)
-{
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-}
diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c
deleted file mode 100644
index db2827b..0000000
--- a/src/superio/winbond/w83627hf/early_serial.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- * Copyright (C) 2010 Win Enterprises (anishp at win-ent.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627hf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-void w83627hf_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
-
-void w83627hf_set_clksel_48(device_t dev)
-{
-	u8 reg8;
-
-	pnp_enter_ext_func_mode(dev);
-	reg8 = pnp_read_config(dev, 0x24);
-	reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
-	pnp_write_config(dev, 0x24, reg8);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c
deleted file mode 100644
index 8ba1a30..0000000
--- a/src/superio/winbond/w83627thg/early_serial.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627thg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void inline w83627thg_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
-
-#ifndef __ROMCC__
-void w83627thg_set_clksel_48(device_t dev) {
-	u8 reg8;
-	pnp_enter_ext_func_mode(dev);
-	reg8 = pnp_read_config(dev, 0x24);
-	reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
-	pnp_write_config(dev, 0x24, reg8);
-	pnp_exit_ext_func_mode(dev);
-}
-#endif
diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c
deleted file mode 100644
index bfd08a3..0000000
--- a/src/superio/winbond/w83627uhg/early_serial.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Dynon Avionics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627uhg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-/** Set the input clock to 24 or 48 MHz. */
-static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
-{
-	u8 value;
-
-	value = pnp_read_config(dev, 0x24);
-	value &= ~(1 << 6);
-	if (!speed_24mhz)
-		value |= (1 << 6);
-	pnp_write_config(dev, 0x24, value);
-}
-
-static void w83627uhg_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c
deleted file mode 100644
index e435645..0000000
--- a/src/superio/winbond/w83697hf/early_serial.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Sean Nelson <snelson at nmt.edu>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83697hf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-void w83697hf_set_clksel_48(device_t dev)
-{
-	u8 reg8;
-
-	pnp_enter_ext_func_mode(dev);
-	reg8 = pnp_read_config(dev, 0x24);
-	reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
-	pnp_write_config(dev, 0x24, reg8);
-	pnp_exit_ext_func_mode(dev);
-}
-
-static void w83697hf_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c
deleted file mode 100644
index c572dcb..0000000
--- a/src/superio/winbond/w83977f/early_serial.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83977f.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void w83977f_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c
deleted file mode 100644
index c016515..0000000
--- a/src/superio/winbond/w83977tf/early_serial.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 AG Electronics Ltd.
- * Copyright (C) 2003-2004 Linux Networx
- * Copyright (C) 2004 Tyan
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83977tf.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0x87, port);
-	outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
-	u16 port = dev >> 8;
-	outb(0xaa, port);
-}
-
-static void w83977tf_enable_serial(device_t dev, u16 iobase)
-{
-	pnp_enter_ext_func_mode(dev);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
-	pnp_set_enable(dev, 1);
-	pnp_exit_ext_func_mode(dev);
-}



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