[coreboot-gerrit] Patch set updated for coreboot: 58f979d ec: Add romstage function for checking and rebooting EC

[Gabe Black (gabeblack@chromium.org)]

Gabe Black (gabeblack at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3744

-gerrit

commit 58f979db54b966392b95b1e2716f419e9c6835d5
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jun 4 10:03:34 2013 -0700

    ec: Add romstage function for checking and rebooting EC
    
    Now that we are executing VbInit() in coreboot we can end up
    in a situation where the recovery reason is consumed during
    VbInit (end of romstage) and then the EC is rebooted to RO
    during ramstage EC init, thereby losing the recovery reason.
    
    Two possiblities are to remove the EC check+reboot from ramstage
    and let it happen in depthcharge.  This however means that the
    system has to boot all the way into depthcharge and then reboot
    the EC and the system again.
    
    Instead if we do a check in romstage before VbInit() is called
    then we can reboot the EC into RO early and avoid booting all
    the way to depthcharge first.
    
    This change adds a ramstage version the EC init function and
    calls it from the shared romstage code immediately after the
    PCH decode windows are setup.
    
    Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/cpu/intel/haswell/romstage.c |  8 ++++++++
 src/ec/google/chromeec/ec.c      | 39 +++++++++++++++++++++++++++++++++++++--
 src/ec/google/chromeec/ec.h      |  1 +
 3 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 8196273..0cef888 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -38,6 +38,9 @@
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include <ec/google/chromeec/ec.h>
+#endif
 #include "haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/raminit.h"
@@ -216,6 +219,11 @@ void romstage_common(const struct romstage_params *params)
 
 	wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
 
+#if CONFIG_EC_GOOGLE_CHROMEEC
+	/* Ensure the EC is in the right mode for recovery */
+	google_chromeec_early_init();
+#endif
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(params->bist);
 
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index d94338f..9b848c0 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -21,12 +21,12 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <delay.h>
+#include <arch/hlt.h>
+#include <reset.h>
 #ifndef __PRE_RAM__
 #include <elog.h>
 #include <stdlib.h>
 #include <string.h>
-#include <reset.h>
-#include <arch/hlt.h>
 #include "chip.h"
 #endif
 #include "ec.h"
@@ -99,6 +99,41 @@ u32 google_chromeec_get_events_b(void)
 	return google_chromeec_get_mask(EC_CMD_HOST_EVENT_GET_B);
 }
 
+#ifndef __SMM__
+/* Check for recovery mode and ensure EC is in RO */
+void google_chromeec_early_init(void)
+{
+	struct chromeec_command cec_cmd;
+	struct ec_response_get_version cec_resp = {{0}};
+
+	cec_cmd.cmd_code = EC_CMD_GET_VERSION;
+	cec_cmd.cmd_version = 0;
+	cec_cmd.cmd_data_out = &cec_resp;
+	cec_cmd.cmd_size_in = 0;
+	cec_cmd.cmd_size_out = sizeof(cec_resp);
+	google_chromeec_command(&cec_cmd);
+
+	if (cec_cmd.cmd_code ||
+	    (recovery_mode_enabled() &&
+	     (cec_resp.current_image != EC_IMAGE_RO))) {
+		struct ec_params_reboot_ec reboot_ec;
+		/* Reboot the EC and make it come back in RO mode */
+		reboot_ec.cmd = EC_REBOOT_COLD;
+		reboot_ec.flags = 0;
+		cec_cmd.cmd_code = EC_CMD_REBOOT_EC;
+		cec_cmd.cmd_version = 0;
+		cec_cmd.cmd_data_in = &reboot_ec;
+		cec_cmd.cmd_size_in = sizeof(reboot_ec);
+		cec_cmd.cmd_size_out = 0; /* ignore response, if any */
+		printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
+		google_chromeec_command(&cec_cmd);
+		udelay(1000);
+		hard_reset();
+		hlt();
+	}
+}
+#endif /* ! __SMM__ */
+
 #ifndef __PRE_RAM__
 
 static int google_chromeec_set_mask(u8 type, u32 mask)
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index 3eb555c..7679a8b 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void);
 void google_chromeec_init(void);
 #endif
 
+void google_chromeec_early_init(void);
 uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size);
 u32 google_chromeec_get_events_b(void);
 int google_chromeec_kbbacklight(int percent);