[coreboot-gerrit] Patch set updated for coreboot: 630741b AMD Kabini: Modify Hudson southbridge to support new AMD processor
Bruce Griffith (Bruce.Griffith@se-eng.com)
gerrit at coreboot.org
Thu Jul 25 09:22:28 CEST 2013
Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3783
-gerrit
commit 630741b6a179e89249c751ecf8fa0d926d7047e1
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date: Tue Jul 9 17:32:42 2013 +0800
AMD Kabini: Modify Hudson southbridge to support new AMD processor
Yangtze uses Hudson AGESA wrapper code but has some changes.
The changes are necessary and have no effects on Hudson.
Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d
Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith at se-eng.com>
---
src/southbridge/amd/Makefile.inc | 1 +
src/southbridge/amd/agesa/Makefile.inc | 1 +
src/southbridge/amd/agesa/hudson/Kconfig | 25 ++++++++++++++++++++-----
src/southbridge/amd/agesa/hudson/early_setup.c | 3 +++
src/southbridge/amd/agesa/hudson/sata.c | 6 ++++++
src/southbridge/amd/agesa/hudson/sm.c | 1 +
src/southbridge/amd/agesa/hudson/spi.c | 9 +++++++++
7 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index cce4702..9ec0171 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -15,6 +15,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
ifeq ($(CONFIG_CPU_AMD_AGESA), y)
diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc
index 822c6fd..fdd5d80 100644
--- a/src/southbridge/amd/agesa/Makefile.inc
+++ b/src/southbridge/amd/agesa/Makefile.inc
@@ -17,3 +17,4 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index af305ee..5cb1722 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -23,7 +23,13 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_USBDEBUG
select HAVE_HARD_RESET
-if SOUTHBRIDGE_AMD_AGESA_HUDSON
+config SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ bool
+ select IOAPIC
+ select HAVE_USBDEBUG
+ select HAVE_HARD_RESET
+
+if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
@@ -72,17 +78,20 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/xhci.bin"
+ default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/imc.bin"
+ default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/gec.bin"
+ default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM
config HUDSON_FWM
@@ -232,4 +241,10 @@ config HUDSON_LEGACY_FREE
Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.
-endif # SOUTHBRIDGE_AMD_AGESA_HUDSON
+endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
+
+if SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ config AMD_SB_SPI_TX_LEN
+ int
+ default 64
+endif
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a0319ab..af5bcbd 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -46,6 +46,9 @@ void hudson_lpc_port80(void)
byte = pci_read_config8(dev, 0x4a);
byte |= 1 << 5; /* enable port 80 */
pci_write_config8(dev, 0x4a, byte);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */
+ pci_write_config8(dev, 0x48, byte);
}
int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c
index cc8bf95..bc1cd92 100644
--- a/src/southbridge/amd/agesa/hudson/sata.c
+++ b/src/southbridge/amd/agesa/hudson/sata.c
@@ -49,3 +49,9 @@ static const struct pci_driver sata0_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_SATA,
};
+
+static const struct pci_driver sata0_driver_ahci __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI,
+};
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index 3b727b9..d6ca215 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -82,6 +82,7 @@
static void sm_init(device_t dev)
{
+ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
}
static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 1a63ce2..b89ea5d 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -61,7 +61,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
/* First byte is cmd which can not being sent through FIFO. */
u8 cmd = *(u8 *)dout++;
u8 readoffby1;
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
u8 readwrite;
+#endif
u8 bytesout, bytesin;
u8 count;
@@ -71,8 +73,15 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ write8(spibar + 0x1E, 5);
+ write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
+ write8(spibar + 0x1E, 6);
+ write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */
+#else
readwrite = (bytesin + readoffby1) << 4 | bytesout;
write8(spibar + 1, readwrite);
+#endif
write8(spibar + 0, cmd);
reset_internal_fifo_pointer();
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