[coreboot-gerrit] New patch to review for coreboot: 19fa92c qemu: move i440fx bits

Gerd Hoffmann (kraxel@redhat.com) gerrit at coreboot.org
Mon Jun 10 16:36:02 CEST 2013


Gerd Hoffmann (kraxel at redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3429

-gerrit

commit 19fa92c9a632469eb1bbe4c763bdccc7e1346a7b
Author: Gerd Hoffmann <kraxel at redhat.com>
Date:   Fri Jun 7 15:46:23 2013 +0200

    qemu: move i440fx bits
    
    Prepare tree for adding q35 support:  Create a new qemu-i440fx directory
    in mainboard/emulation.  Move over most bits from qemu-x86.  Leave a few
    files which I expect can be shared between i440fx and q35 support in the
    qemu-x86 directory.
    
    Change-Id: Ib8c58175c5734cfcda1b22404ef52c09d38f0462
    Signed-off-by: Gerd Hoffmann <kraxel at redhat.com>
---
 src/mainboard/emulation/Kconfig                   |  11 +-
 src/mainboard/emulation/qemu-i440fx/Kconfig       |  37 +++
 src/mainboard/emulation/qemu-i440fx/Makefile.inc  |   3 +
 src/mainboard/emulation/qemu-i440fx/acpi_tables.c | 189 ++++++++++++
 src/mainboard/emulation/qemu-i440fx/cmos.layout   |  74 +++++
 src/mainboard/emulation/qemu-i440fx/devicetree.cb |  18 ++
 src/mainboard/emulation/qemu-i440fx/dsdt.asl      | 347 ++++++++++++++++++++++
 src/mainboard/emulation/qemu-i440fx/irq_tables.c  |  35 +++
 src/mainboard/emulation/qemu-i440fx/mainboard.c   |  65 ++++
 src/mainboard/emulation/qemu-i440fx/romstage.c    |  61 ++++
 src/mainboard/emulation/qemu-x86/Kconfig          |  37 ---
 src/mainboard/emulation/qemu-x86/Makefile.inc     |   3 -
 src/mainboard/emulation/qemu-x86/acpi_tables.c    | 189 ------------
 src/mainboard/emulation/qemu-x86/cmos.layout      |  74 -----
 src/mainboard/emulation/qemu-x86/devicetree.cb    |  18 --
 src/mainboard/emulation/qemu-x86/dsdt.asl         | 347 ----------------------
 src/mainboard/emulation/qemu-x86/irq_tables.c     |  35 ---
 src/mainboard/emulation/qemu-x86/mainboard.c      |  65 ----
 src/mainboard/emulation/qemu-x86/northbridge.c    |   4 +-
 src/mainboard/emulation/qemu-x86/romstage.c       |  61 ----
 20 files changed, 839 insertions(+), 834 deletions(-)

diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig
index ea6b180..72b70af 100644
--- a/src/mainboard/emulation/Kconfig
+++ b/src/mainboard/emulation/Kconfig
@@ -3,15 +3,20 @@ if VENDOR_EMULATION
 choice
 	prompt "Mainboard model"
 
-config BOARD_EMULATION_QEMU_X86
-	bool "QEMU x86"
+config BOARD_EMULATION_QEMU_X86_I440FX
+	bool "QEMU x86 i440fx/piix4 (aka qemu -M pc)"
 
 config BOARD_EMULATION_QEMU_ARMV7
 	bool "QEMU armv7 (vexpress-a9)"
 
 endchoice
 
-source "src/mainboard/emulation/qemu-x86/Kconfig"
+config BOARD_EMULATION_QEMU_X86
+	bool
+	default y
+	depends on BOARD_EMULATION_QEMU_X86_I440FX
+
+source "src/mainboard/emulation/qemu-i440fx/Kconfig"
 source "src/mainboard/emulation/qemu-armv7/Kconfig"
 
 config MAINBOARD_VENDOR
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
new file mode 100644
index 0000000..a61050a
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_EMULATION_QEMU_X86_I440FX
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_QEMU_X86
+	select SOUTHBRIDGE_INTEL_I82371EB
+	select CACHE_AS_RAM
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select BOARD_ROMSIZE_KB_256
+	select EARLY_CBMEM_INIT
+
+config MAINBOARD_DIR
+	string
+	default emulation/qemu-i440fx
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "QEMU x86 i440fx/piix4"
+
+config IRQ_SLOT_COUNT
+	int
+	default 6
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xd0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+
+endif # BOARD_EMULATION_QEMU_X86
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
new file mode 100644
index 0000000..2365d28
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc
@@ -0,0 +1,3 @@
+cpu_incs += $(src)/mainboard/emulation/qemu-x86/cache_as_ram.inc
+ramstage-y += ../qemu-x86/northbridge.c
+ramstage-y += ../qemu-x86/fw_cfg.c
diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c
new file mode 100644
index 0000000..904fe0f
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout
new file mode 100644
index 0000000..c1354a2
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --git a/src/mainboard/emulation/qemu-i440fx/devicetree.cb b/src/mainboard/emulation/qemu-i440fx/devicetree.cb
new file mode 100644
index 0000000..a4fcef1
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/devicetree.cb
@@ -0,0 +1,18 @@
+chip mainboard/emulation/qemu-i440fx
+	device cpu_cluster 0 on
+		chip cpu/qemu-x86
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		device pci 0.0 on end		# northbridge (i440fx)
+		chip southbridge/intel/i82371eb # southbridge
+			device pci 01.0 on end	# ISA bridge
+			device pci 01.1 on end	# IDE
+			device pci 01.3 on end	# ACPI
+			register "ide0_enable" = "1"
+			register "ide1_enable" = "1"
+			register "gpo" = "0x7fffbbff"
+		end
+	end
+end
diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
new file mode 100644
index 0000000..1ca3dd8
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
@@ -0,0 +1,347 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+DefinitionBlock (
+    "dsdt.aml",         // Output Filename
+    "DSDT",             // Signature
+    0x01,               // DSDT Compliance Revision
+    "CORE",             // OEMID
+    "COREBOOT",         // TABLE ID
+    0x1                 // OEM Revision
+    )
+{
+
+#include "../qemu-x86/acpi/dbug.asl"
+
+
+/****************************************************************
+ * PCI Bus definition
+ ****************************************************************/
+
+    Scope(\_SB) {
+        Device(PCI0) {
+            Name(_HID, EisaId("PNP0A03"))
+            Name(_ADR, 0x00)
+            Name(_UID, 1)
+        }
+    }
+
+#include "../qemu-x86/acpi/pci-crs.asl"
+#include "../qemu-x86/acpi/hpet.asl"
+
+
+/****************************************************************
+ * VGA
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(VGA) {
+            Name(_ADR, 0x00020000)
+            OperationRegion(PCIC, PCI_Config, Zero, 0x4)
+            Field(PCIC, DWordAcc, NoLock, Preserve) {
+                VEND, 32
+            }
+            Method(_S1D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S2D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S3D, 0, NotSerialized) {
+                If (LEqual(VEND, 0x1001b36)) {
+                    Return (0x03)           // QXL
+                } Else {
+                    Return (0x00)
+                }
+            }
+        }
+    }
+
+
+/****************************************************************
+ * PIIX4 PM
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(PX13) {
+            Name(_ADR, 0x00010003)
+            OperationRegion(P13C, PCI_Config, 0x00, 0xff)
+        }
+    }
+
+
+/****************************************************************
+ * PIIX3 ISA bridge
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(ISA) {
+            Name(_ADR, 0x00010000)
+
+            /* PIIX PCI to ISA irq remapping */
+            OperationRegion(P40C, PCI_Config, 0x60, 0x04)
+
+            /* enable bits */
+            Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
+                Offset(0x5f),
+                , 7,
+                LPEN, 1,         // LPT
+                Offset(0x67),
+                , 3,
+                CAEN, 1,         // COM1
+                , 3,
+                CBEN, 1,         // COM2
+            }
+            Name(FDEN, 1)
+        }
+    }
+
+#include "../qemu-x86/acpi/isa.asl"
+
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        OperationRegion(PCST, SystemIO, 0xae00, 0x08)
+        Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
+            PCIU, 32,
+            PCID, 32,
+        }
+
+        OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
+        Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
+            B0EJ, 32,
+        }
+
+        /* Methods called by bulk generated PCI devices below */
+
+        /* Methods called by hotplug devices */
+        Method(PCEJ, 1, NotSerialized) {
+            // _EJ0 method - eject callback
+            Store(ShiftLeft(1, Arg0), B0EJ)
+            Return (0x0)
+        }
+
+        /* Hotplug notification method supplied by SSDT */
+        External(\_SB.PCI0.PCNT, MethodObj)
+
+        /* PCI hotplug notify method */
+        Method(PCNF, 0) {
+            // Local0 = iterator
+            Store(Zero, Local0)
+            While (LLess(Local0, 31)) {
+                Increment(Local0)
+                If (And(PCIU, ShiftLeft(1, Local0))) {
+                    PCNT(Local0, 1)
+                }
+                If (And(PCID, ShiftLeft(1, Local0))) {
+                    PCNT(Local0, 3)
+                }
+            }
+        }
+    }
+
+
+/****************************************************************
+ * PCI IRQs
+ ****************************************************************/
+
+    Scope(\_SB) {
+        Scope(PCI0) {
+            Name(_PRT, Package() {
+                /* PCI IRQ routing table, example from ACPI 2.0a specification,
+                   section 6.2.8.1 */
+                /* Note: we provide the same info as the PCI routing
+                   table of the Bochs BIOS */
+
+#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
+    Package() { nr##ffff, 0, lnk0, 0 }, \
+    Package() { nr##ffff, 1, lnk1, 0 }, \
+    Package() { nr##ffff, 2, lnk2, 0 }, \
+    Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
+
+                prt_slot0(0x0000),
+                /* Device 1 is power mgmt device, and can only use irq 9 */
+                prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
+                prt_slot2(0x0002),
+                prt_slot3(0x0003),
+                prt_slot0(0x0004),
+                prt_slot1(0x0005),
+                prt_slot2(0x0006),
+                prt_slot3(0x0007),
+                prt_slot0(0x0008),
+                prt_slot1(0x0009),
+                prt_slot2(0x000a),
+                prt_slot3(0x000b),
+                prt_slot0(0x000c),
+                prt_slot1(0x000d),
+                prt_slot2(0x000e),
+                prt_slot3(0x000f),
+                prt_slot0(0x0010),
+                prt_slot1(0x0011),
+                prt_slot2(0x0012),
+                prt_slot3(0x0013),
+                prt_slot0(0x0014),
+                prt_slot1(0x0015),
+                prt_slot2(0x0016),
+                prt_slot3(0x0017),
+                prt_slot0(0x0018),
+                prt_slot1(0x0019),
+                prt_slot2(0x001a),
+                prt_slot3(0x001b),
+                prt_slot0(0x001c),
+                prt_slot1(0x001d),
+                prt_slot2(0x001e),
+                prt_slot3(0x001f),
+            })
+        }
+
+        Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
+            PRQ0,   8,
+            PRQ1,   8,
+            PRQ2,   8,
+            PRQ3,   8
+        }
+
+        Method(IQST, 1, NotSerialized) {
+            // _STA method - get status
+            If (And(0x80, Arg0)) {
+                Return (0x09)
+            }
+            Return (0x0B)
+        }
+        Method(IQCR, 1, NotSerialized) {
+            // _CRS method - get current settings
+            Name(PRR0, ResourceTemplate() {
+                Interrupt(, Level, ActiveHigh, Shared) { 0 }
+            })
+            CreateDWordField(PRR0, 0x05, PRRI)
+            If (LLess(Arg0, 0x80)) {
+                Store(Arg0, PRRI)
+            }
+            Return (PRR0)
+        }
+
+#define define_link(link, uid, reg)                             \
+        Device(link) {                                          \
+            Name(_HID, EISAID("PNP0C0F"))                       \
+            Name(_UID, uid)                                     \
+            Name(_PRS, ResourceTemplate() {                     \
+                Interrupt(, Level, ActiveHigh, Shared) {        \
+                    5, 10, 11                                   \
+                }                                               \
+            })                                                  \
+            Method(_STA, 0, NotSerialized) {                    \
+                Return (IQST(reg))                              \
+            }                                                   \
+            Method(_DIS, 0, NotSerialized) {                    \
+                Or(reg, 0x80, reg)                              \
+            }                                                   \
+            Method(_CRS, 0, NotSerialized) {                    \
+                Return (IQCR(reg))                              \
+            }                                                   \
+            Method(_SRS, 1, NotSerialized) {                    \
+                CreateDWordField(Arg0, 0x05, PRRI)              \
+                Store(PRRI, reg)                                \
+            }                                                   \
+        }
+
+        define_link(LNKA, 0, PRQ0)
+        define_link(LNKB, 1, PRQ1)
+        define_link(LNKC, 2, PRQ2)
+        define_link(LNKD, 3, PRQ3)
+
+        Device(LNKS) {
+            Name(_HID, EISAID("PNP0C0F"))
+            Name(_UID, 4)
+            Name(_PRS, ResourceTemplate() {
+                Interrupt(, Level, ActiveHigh, Shared) { 9 }
+            })
+
+            // The SCI cannot be disabled and is always attached to GSI 9,
+            // so these are no-ops.  We only need this link to override the
+            // polarity to active high and match the content of the MADT.
+            Method(_STA, 0, NotSerialized) { Return (0x0b) }
+            Method(_DIS, 0, NotSerialized) { }
+            Method(_CRS, 0, NotSerialized) { Return (_PRS) }
+            Method(_SRS, 1, NotSerialized) { }
+        }
+    }
+
+#if 0
+#include "../qemu-x86/acpi/cpu-hotplug.asl"
+#endif
+
+
+/****************************************************************
+ * General purpose events
+ ****************************************************************/
+
+    Scope(\_GPE) {
+        Name(_HID, "ACPI0006")
+
+        Method(_L00) {
+        }
+        Method(_E01) {
+#if 0
+            // PCI hotplug event
+            \_SB.PCI0.PCNF()
+#endif
+        }
+        Method(_E02) {
+#if 0
+            // CPU hotplug event
+            \_SB.PRSC()
+#endif
+        }
+        Method(_L03) {
+        }
+        Method(_L04) {
+        }
+        Method(_L05) {
+        }
+        Method(_L06) {
+        }
+        Method(_L07) {
+        }
+        Method(_L08) {
+        }
+        Method(_L09) {
+        }
+        Method(_L0A) {
+        }
+        Method(_L0B) {
+        }
+        Method(_L0C) {
+        }
+        Method(_L0D) {
+        }
+        Method(_L0E) {
+        }
+        Method(_L0F) {
+        }
+    }
+}
diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c
new file mode 100644
index 0000000..21eeabf
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c
@@ -0,0 +1,35 @@
+/* This file was generated by getpir.c, do not modify!
+   (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x01<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x8086,		 /* Vendor */
+	0x7000,		 /* Device */
+	0,		 /* Miniport data */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x7,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
+		{0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
+		{0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
+		{0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
+		{0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
+	}
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+        return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c
new file mode 100644
index 0000000..f651b99
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer at coreboot.org>
+ * Copyright (C) 2010 Kevin O'Connor <kevin at koconnor.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+
+static const unsigned char qemu_i440fx_irqs[] = {
+	11, 10, 10, 11,
+	11, 10, 10, 11,
+};
+
+static void qemu_nb_init(device_t dev)
+{
+	/* Map memory at 0xc0000 - 0xfffff */
+	int i;
+	uint8_t v = pci_read_config8(dev, 0x59);
+	v |= 0x30;
+	pci_write_config8(dev, 0x59, v);
+	for (i=0; i<6; i++)
+	pci_write_config8(dev, 0x5a + i, 0x33);
+
+	/* This sneaked in here, because Qemu does not
+	 * emulate a SuperIO chip
+	 */
+	pc_keyboard_init(0);
+
+	/* setup IRQ routing */
+	for (i = 0; i < 32; i++)
+		pci_assign_irqs(0, i, qemu_i440fx_irqs + (i % 4));
+}
+
+static struct device_operations nb_operations = {
+ 	.read_resources   = pci_dev_read_resources,
+ 	.set_resources    = pci_dev_set_resources,
+ 	.enable_resources = pci_dev_enable_resources,
+ 	.init             = qemu_nb_init,
+	.ops_pci          = 0,
+};
+
+static const struct pci_driver nb_driver __pci_driver = {
+	.ops = &nb_operations,
+	.vendor = 0x8086,
+	.device = 0x1237,
+};
diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c
new file mode 100644
index 0000000..779fae0
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/romstage.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Stefan Reinauer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <timestamp.h>
+#include "drivers/pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+
+#include "../qemu-x86/memory.c"
+
+void main(unsigned long bist)
+{
+	int cbmem_was_initted;
+
+	/* init_timer(); */
+	post_code(0x05);
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	//print_pci_devices();
+	//dump_pci_devices();
+
+	cbmem_was_initted = !cbmem_initialize();
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(rdtsc());
+	timestamp_add_now(TS_START_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+
+}
diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig
deleted file mode 100644
index f816794..0000000
--- a/src/mainboard/emulation/qemu-x86/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-if BOARD_EMULATION_QEMU_X86
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_QEMU_X86
-	select SOUTHBRIDGE_INTEL_I82371EB
-	select CACHE_AS_RAM
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_ACPI_TABLES
-	select HAVE_ACPI_RESUME
-	select BOARD_ROMSIZE_KB_256
-	select EARLY_CBMEM_INIT
-
-config MAINBOARD_DIR
-	string
-	default emulation/qemu-x86
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "QEMU x86"
-
-config IRQ_SLOT_COUNT
-	int
-	default 6
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xd0000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x10000
-
-
-endif # BOARD_EMULATION_QEMU_X86
diff --git a/src/mainboard/emulation/qemu-x86/Makefile.inc b/src/mainboard/emulation/qemu-x86/Makefile.inc
deleted file mode 100644
index 21d7344..0000000
--- a/src/mainboard/emulation/qemu-x86/Makefile.inc
+++ /dev/null
@@ -1,3 +0,0 @@
-cpu_incs += $(src)/mainboard/emulation/qemu-x86/cache_as_ram.inc
-ramstage-y += northbridge.c
-ramstage-y += fw_cfg.c
diff --git a/src/mainboard/emulation/qemu-x86/acpi_tables.c b/src/mainboard/emulation/qemu-x86/acpi_tables.c
deleted file mode 100644
index 904fe0f..0000000
--- a/src/mainboard/emulation/qemu-x86/acpi_tables.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-
-extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
-unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
-{
-	generate_cpu_entries();
-	return (unsigned long) (acpigen_get_current());
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	/* No NUMA, no SRAT */
-	return current;
-}
-
-#define ALIGN_CURRENT current = (ALIGN(current, 16))
-unsigned long write_acpi_tables(unsigned long start)
-{
-	unsigned long current;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_mcfg_t *mcfg;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
-	acpi_header_t *slic;
-#endif
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
-
-	current = start;
-
-	/* Align ACPI tables to 16byte */
-	ALIGN_CURRENT;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-	ALIGN_CURRENT;
-	xsdt = (acpi_xsdt_t *) current;
-	current += sizeof(acpi_xsdt_t);
-	ALIGN_CURRENT;
-
-	/* clear all table memory */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	ALIGN_CURRENT;
-	acpi_create_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET Timers Linux wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, mcfg);
-
-	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	ALIGN_CURRENT;
-	acpi_create_facs(facs);
-
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-
-	ALIGN_CURRENT;
-
-	/* We patched up the DSDT, so we need to recalculate the checksum */
-	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
-
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-
-#if CONFIG_HAVE_ACPI_SLIC
-	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
-	current += acpi_create_slic(current);
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, slic);
-#endif
-
-	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-	ALIGN_CURRENT;
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
-}
diff --git a/src/mainboard/emulation/qemu-x86/cmos.layout b/src/mainboard/emulation/qemu-x86/cmos.layout
deleted file mode 100644
index c1354a2..0000000
--- a/src/mainboard/emulation/qemu-x86/cmos.layout
+++ /dev/null
@@ -1,74 +0,0 @@
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-386          1       e       1        ECC_memory
-388          4       r       0        reboot_bits
-392          3       e       5        baud_rate
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432          8       h       0        boot_countdown
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-
-checksums
-
-checksum 392 1007 1008
-
-
diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb
deleted file mode 100644
index f37454b..0000000
--- a/src/mainboard/emulation/qemu-x86/devicetree.cb
+++ /dev/null
@@ -1,18 +0,0 @@
-chip mainboard/emulation/qemu-x86
-	device cpu_cluster 0 on
-		chip cpu/qemu-x86
-			device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		device pci 0.0 on end		# northbridge (i440fx)
-		chip southbridge/intel/i82371eb # southbridge
-			device pci 01.0 on end	# ISA bridge
-			device pci 01.1 on end	# IDE
-			device pci 01.3 on end	# ACPI
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
-			register "gpo" = "0x7fffbbff"
-		end
-	end
-end
diff --git a/src/mainboard/emulation/qemu-x86/dsdt.asl b/src/mainboard/emulation/qemu-x86/dsdt.asl
deleted file mode 100644
index e63d10f..0000000
--- a/src/mainboard/emulation/qemu-x86/dsdt.asl
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * Bochs/QEMU ACPI DSDT ASL definition
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License version 2 as published by the Free Software Foundation.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-DefinitionBlock (
-    "dsdt.aml",         // Output Filename
-    "DSDT",             // Signature
-    0x01,               // DSDT Compliance Revision
-    "CORE",             // OEMID
-    "COREBOOT",         // TABLE ID
-    0x1                 // OEM Revision
-    )
-{
-
-#include "acpi/dbug.asl"
-
-
-/****************************************************************
- * PCI Bus definition
- ****************************************************************/
-
-    Scope(\_SB) {
-        Device(PCI0) {
-            Name(_HID, EisaId("PNP0A03"))
-            Name(_ADR, 0x00)
-            Name(_UID, 1)
-        }
-    }
-
-#include "acpi/pci-crs.asl"
-#include "acpi/hpet.asl"
-
-
-/****************************************************************
- * VGA
- ****************************************************************/
-
-    Scope(\_SB.PCI0) {
-        Device(VGA) {
-            Name(_ADR, 0x00020000)
-            OperationRegion(PCIC, PCI_Config, Zero, 0x4)
-            Field(PCIC, DWordAcc, NoLock, Preserve) {
-                VEND, 32
-            }
-            Method(_S1D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S2D, 0, NotSerialized) {
-                Return (0x00)
-            }
-            Method(_S3D, 0, NotSerialized) {
-                If (LEqual(VEND, 0x1001b36)) {
-                    Return (0x03)           // QXL
-                } Else {
-                    Return (0x00)
-                }
-            }
-        }
-    }
-
-
-/****************************************************************
- * PIIX4 PM
- ****************************************************************/
-
-    Scope(\_SB.PCI0) {
-        Device(PX13) {
-            Name(_ADR, 0x00010003)
-            OperationRegion(P13C, PCI_Config, 0x00, 0xff)
-        }
-    }
-
-
-/****************************************************************
- * PIIX3 ISA bridge
- ****************************************************************/
-
-    Scope(\_SB.PCI0) {
-        Device(ISA) {
-            Name(_ADR, 0x00010000)
-
-            /* PIIX PCI to ISA irq remapping */
-            OperationRegion(P40C, PCI_Config, 0x60, 0x04)
-
-            /* enable bits */
-            Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
-                Offset(0x5f),
-                , 7,
-                LPEN, 1,         // LPT
-                Offset(0x67),
-                , 3,
-                CAEN, 1,         // COM1
-                , 3,
-                CBEN, 1,         // COM2
-            }
-            Name(FDEN, 1)
-        }
-    }
-
-#include "acpi/isa.asl"
-
-
-/****************************************************************
- * PCI hotplug
- ****************************************************************/
-
-    Scope(\_SB.PCI0) {
-        OperationRegion(PCST, SystemIO, 0xae00, 0x08)
-        Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
-            PCIU, 32,
-            PCID, 32,
-        }
-
-        OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
-        Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
-            B0EJ, 32,
-        }
-
-        /* Methods called by bulk generated PCI devices below */
-
-        /* Methods called by hotplug devices */
-        Method(PCEJ, 1, NotSerialized) {
-            // _EJ0 method - eject callback
-            Store(ShiftLeft(1, Arg0), B0EJ)
-            Return (0x0)
-        }
-
-        /* Hotplug notification method supplied by SSDT */
-        External(\_SB.PCI0.PCNT, MethodObj)
-
-        /* PCI hotplug notify method */
-        Method(PCNF, 0) {
-            // Local0 = iterator
-            Store(Zero, Local0)
-            While (LLess(Local0, 31)) {
-                Increment(Local0)
-                If (And(PCIU, ShiftLeft(1, Local0))) {
-                    PCNT(Local0, 1)
-                }
-                If (And(PCID, ShiftLeft(1, Local0))) {
-                    PCNT(Local0, 3)
-                }
-            }
-        }
-    }
-
-
-/****************************************************************
- * PCI IRQs
- ****************************************************************/
-
-    Scope(\_SB) {
-        Scope(PCI0) {
-            Name(_PRT, Package() {
-                /* PCI IRQ routing table, example from ACPI 2.0a specification,
-                   section 6.2.8.1 */
-                /* Note: we provide the same info as the PCI routing
-                   table of the Bochs BIOS */
-
-#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
-    Package() { nr##ffff, 0, lnk0, 0 }, \
-    Package() { nr##ffff, 1, lnk1, 0 }, \
-    Package() { nr##ffff, 2, lnk2, 0 }, \
-    Package() { nr##ffff, 3, lnk3, 0 }
-
-#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
-#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
-
-                prt_slot0(0x0000),
-                /* Device 1 is power mgmt device, and can only use irq 9 */
-                prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
-                prt_slot2(0x0002),
-                prt_slot3(0x0003),
-                prt_slot0(0x0004),
-                prt_slot1(0x0005),
-                prt_slot2(0x0006),
-                prt_slot3(0x0007),
-                prt_slot0(0x0008),
-                prt_slot1(0x0009),
-                prt_slot2(0x000a),
-                prt_slot3(0x000b),
-                prt_slot0(0x000c),
-                prt_slot1(0x000d),
-                prt_slot2(0x000e),
-                prt_slot3(0x000f),
-                prt_slot0(0x0010),
-                prt_slot1(0x0011),
-                prt_slot2(0x0012),
-                prt_slot3(0x0013),
-                prt_slot0(0x0014),
-                prt_slot1(0x0015),
-                prt_slot2(0x0016),
-                prt_slot3(0x0017),
-                prt_slot0(0x0018),
-                prt_slot1(0x0019),
-                prt_slot2(0x001a),
-                prt_slot3(0x001b),
-                prt_slot0(0x001c),
-                prt_slot1(0x001d),
-                prt_slot2(0x001e),
-                prt_slot3(0x001f),
-            })
-        }
-
-        Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
-            PRQ0,   8,
-            PRQ1,   8,
-            PRQ2,   8,
-            PRQ3,   8
-        }
-
-        Method(IQST, 1, NotSerialized) {
-            // _STA method - get status
-            If (And(0x80, Arg0)) {
-                Return (0x09)
-            }
-            Return (0x0B)
-        }
-        Method(IQCR, 1, NotSerialized) {
-            // _CRS method - get current settings
-            Name(PRR0, ResourceTemplate() {
-                Interrupt(, Level, ActiveHigh, Shared) { 0 }
-            })
-            CreateDWordField(PRR0, 0x05, PRRI)
-            If (LLess(Arg0, 0x80)) {
-                Store(Arg0, PRRI)
-            }
-            Return (PRR0)
-        }
-
-#define define_link(link, uid, reg)                             \
-        Device(link) {                                          \
-            Name(_HID, EISAID("PNP0C0F"))                       \
-            Name(_UID, uid)                                     \
-            Name(_PRS, ResourceTemplate() {                     \
-                Interrupt(, Level, ActiveHigh, Shared) {        \
-                    5, 10, 11                                   \
-                }                                               \
-            })                                                  \
-            Method(_STA, 0, NotSerialized) {                    \
-                Return (IQST(reg))                              \
-            }                                                   \
-            Method(_DIS, 0, NotSerialized) {                    \
-                Or(reg, 0x80, reg)                              \
-            }                                                   \
-            Method(_CRS, 0, NotSerialized) {                    \
-                Return (IQCR(reg))                              \
-            }                                                   \
-            Method(_SRS, 1, NotSerialized) {                    \
-                CreateDWordField(Arg0, 0x05, PRRI)              \
-                Store(PRRI, reg)                                \
-            }                                                   \
-        }
-
-        define_link(LNKA, 0, PRQ0)
-        define_link(LNKB, 1, PRQ1)
-        define_link(LNKC, 2, PRQ2)
-        define_link(LNKD, 3, PRQ3)
-
-        Device(LNKS) {
-            Name(_HID, EISAID("PNP0C0F"))
-            Name(_UID, 4)
-            Name(_PRS, ResourceTemplate() {
-                Interrupt(, Level, ActiveHigh, Shared) { 9 }
-            })
-
-            // The SCI cannot be disabled and is always attached to GSI 9,
-            // so these are no-ops.  We only need this link to override the
-            // polarity to active high and match the content of the MADT.
-            Method(_STA, 0, NotSerialized) { Return (0x0b) }
-            Method(_DIS, 0, NotSerialized) { }
-            Method(_CRS, 0, NotSerialized) { Return (_PRS) }
-            Method(_SRS, 1, NotSerialized) { }
-        }
-    }
-
-#if 0
-#include "acpi/cpu-hotplug.asl"
-#endif
-
-
-/****************************************************************
- * General purpose events
- ****************************************************************/
-
-    Scope(\_GPE) {
-        Name(_HID, "ACPI0006")
-
-        Method(_L00) {
-        }
-        Method(_E01) {
-#if 0
-            // PCI hotplug event
-            \_SB.PCI0.PCNF()
-#endif
-        }
-        Method(_E02) {
-#if 0
-            // CPU hotplug event
-            \_SB.PRSC()
-#endif
-        }
-        Method(_L03) {
-        }
-        Method(_L04) {
-        }
-        Method(_L05) {
-        }
-        Method(_L06) {
-        }
-        Method(_L07) {
-        }
-        Method(_L08) {
-        }
-        Method(_L09) {
-        }
-        Method(_L0A) {
-        }
-        Method(_L0B) {
-        }
-        Method(_L0C) {
-        }
-        Method(_L0D) {
-        }
-        Method(_L0E) {
-        }
-        Method(_L0F) {
-        }
-    }
-}
diff --git a/src/mainboard/emulation/qemu-x86/irq_tables.c b/src/mainboard/emulation/qemu-x86/irq_tables.c
deleted file mode 100644
index 21eeabf..0000000
--- a/src/mainboard/emulation/qemu-x86/irq_tables.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/* This file was generated by getpir.c, do not modify!
-   (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x01<<3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x7000,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x7,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
-		{0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
-		{0x00,(0x04<<3)|0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
-		{0x00,(0x05<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
-		{0x00,(0x06<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
-	}
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-        return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c
deleted file mode 100644
index f651b99..0000000
--- a/src/mainboard/emulation/qemu-x86/mainboard.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer at coreboot.org>
- * Copyright (C) 2010 Kevin O'Connor <kevin at koconnor.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/keyboard.h>
-#include <arch/io.h>
-
-static const unsigned char qemu_i440fx_irqs[] = {
-	11, 10, 10, 11,
-	11, 10, 10, 11,
-};
-
-static void qemu_nb_init(device_t dev)
-{
-	/* Map memory at 0xc0000 - 0xfffff */
-	int i;
-	uint8_t v = pci_read_config8(dev, 0x59);
-	v |= 0x30;
-	pci_write_config8(dev, 0x59, v);
-	for (i=0; i<6; i++)
-	pci_write_config8(dev, 0x5a + i, 0x33);
-
-	/* This sneaked in here, because Qemu does not
-	 * emulate a SuperIO chip
-	 */
-	pc_keyboard_init(0);
-
-	/* setup IRQ routing */
-	for (i = 0; i < 32; i++)
-		pci_assign_irqs(0, i, qemu_i440fx_irqs + (i % 4));
-}
-
-static struct device_operations nb_operations = {
- 	.read_resources   = pci_dev_read_resources,
- 	.set_resources    = pci_dev_set_resources,
- 	.enable_resources = pci_dev_enable_resources,
- 	.init             = qemu_nb_init,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver nb_driver __pci_driver = {
-	.ops = &nb_operations,
-	.vendor = 0x8086,
-	.device = 0x1237,
-};
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index 992a39e..c2e4ba2 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -185,7 +185,7 @@ static void northbridge_enable(struct device *dev)
 	}
 }
 
-struct chip_operations mainboard_emulation_qemu_x86_ops = {
-	CHIP_NAME("QEMU Northbridge")
+struct chip_operations mainboard_emulation_qemu_i440fx_ops = {
+	CHIP_NAME("QEMU Northbridge i440fx")
 	.enable_dev = northbridge_enable,
 };
diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c
deleted file mode 100644
index 3faf947..0000000
--- a/src/mainboard/emulation/qemu-x86/romstage.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Stefan Reinauer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/hlt.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <timestamp.h>
-#include "drivers/pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-
-#include "memory.c"
-
-void main(unsigned long bist)
-{
-	int cbmem_was_initted;
-
-	/* init_timer(); */
-	post_code(0x05);
-
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	//print_pci_devices();
-	//dump_pci_devices();
-
-	cbmem_was_initted = !cbmem_initialize();
-#if CONFIG_COLLECT_TIMESTAMPS
-	timestamp_init(rdtsc());
-	timestamp_add_now(TS_START_ROMSTAGE);
-#endif
-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
-
-}



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