[coreboot-gerrit] Patch merged into coreboot/master: 0d8d482 AMD S3 resume: Add framwork to write bigger data

gerrit at coreboot.org gerrit at coreboot.org
Sat Jun 29 18:57:43 CEST 2013

the following patch was just integrated into master:
commit 0d8d482f6316885d7e553d9aeb538ce5bbd2fbba
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Sat Jun 8 10:25:06 2013 +0800

    AMD S3 resume: Add framwork to write bigger data
    This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]
    Some AMD south bridge can write bigger data when saving S3 info.
    In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size.
    AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig'
    and then can be overridden in the Kconfig for specific
    southbridges that support larger size.
    I have tested on AMD Parmer and Thatcher. We will release a new board
    whose south bridge can transfer more than 4 bytes each time.
    [1] http://review.coreboot.org/#/c/2306/
    Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
    Reviewed-on: http://review.coreboot.org/3413
    Tested-by: build bot (Jenkins)
    Reviewed-by: Bruce Griffith <Bruce.Griffith at se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

See http://review.coreboot.org/3413 for details.


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