[coreboot-gerrit] Patch merged into coreboot/master: 467f31d haswell/lynxpoint: Use new PCH/PM helper functions

gerrit at coreboot.org gerrit at coreboot.org
Thu Mar 21 23:11:26 CET 2013

the following patch was just integrated into master:
commit 467f31de92ca2ed9df1530270e9aabdd69fe8f88
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Mar 8 17:00:37 2013 -0800

    haswell/lynxpoint: Use new PCH/PM helper functions
    This makes use of the new functions from pmutil.c that take
    care of the differences between -H and -LP chipsets.
    It also adds support for the LynxPoint-LP GPE0 register block
    and the SMI/SCI routing differences.
    The FADT is updated to report the new 256 byte GPE0 block on
    wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
    block so that part is zeroed to prevent IASL and the kernel
    from complaining about a mismatch.
    This was tested on WTM2.  Unfortunately I am still unable to get an
    SCI delivered from the EC but I suspect that is due to a magic
    command needed to put the EC in ACPI mode.  Instead I verified that
    all of the power management and GPIO registers were set to expected
    I also tested transitions into S3 and S5 from both the kernel and
    by pressing the power button at the developer mode screen and they
    all function as expected.
    Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/2816
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Mar 19 21:46:23 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Thu Mar 21 23:11:25 2013, giving +2
See http://review.coreboot.org/2816 for details.


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