[coreboot-gerrit] New patch to review for coreboot: 3f476d8 resources: introduce reserved_ram_resource()

[Aaron Durbin (adurbin@google.com)]

Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2886

-gerrit

commit 3f476d86eab0f1d458b77be1f9f92a6f92d8d6b8
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Mar 22 22:03:09 2013 -0500

    resources: introduce reserved_ram_resource()
    
    mmio_resource() was previously being used for reserving
    RAM from the OS by using IORESOURCE_IGNORE_MTRR atrribute.
    Instead, be more explicit for those uses with
    reserved_ram_resource(). bad_ram_resource() now calls
    reserved_ram_resource(). Those resources are marked as cacheable
    but reserved.
    
    The sandybridge and haswell code were relying on the implementation
    fo the MTRR algorithm's interaction for reserved regions. Instead
    be explicit about what ranges are MMIO reserved and what are RAM
    reserved.
    
    Change-Id: I1e47026970fb37c0305e4d49a12c98b0cdd1abe5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/include/device/device.h                     |  5 ++++-
 src/northbridge/intel/haswell/northbridge.c     | 21 ++++++++++-----------
 src/northbridge/intel/sandybridge/northbridge.c |  8 ++++++--
 3 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/src/include/device/device.h b/src/include/device/device.h
index 5219310..b8dfbf5 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -206,8 +206,11 @@ void fixed_mem_resource(device_t dev, unsigned long index,
 #define ram_resource(dev, idx, basek, sizek) \
 	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
 
+#define reserved_ram_resource(dev, idx, basek, sizek) \
+	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+
 #define bad_ram_resource(dev, idx, basek, sizek) \
-	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_IGNORE_MTRR)
+	reserved_ram_resource((dev), (idx), (basek), (sizek))
 
 #define uma_resource(dev, idx, basek, sizek) \
 	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB)
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index b57b28e..16196ad 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -53,15 +53,6 @@ int bridge_silicon_revision(void)
 	return bridge_revision_id;
 }
 
-/* Reserve everything between A segment and 1MB:
- *
- * 0xa0000 - 0xbffff: legacy VGA
- * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
- * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
- */
-static const int legacy_hole_base_k = 0xa0000 / 1024;
-static const int legacy_hole_size_k = 384;
-
 void cbmem_post_handling(void)
 {
 	update_mrc_cache();
@@ -414,9 +405,17 @@ static void mc_add_dram_resources(device_t dev)
 	if (size_k > 0)
 		ram_resource(dev, index++, base_k, size_k);
 
-	mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
+	/* Reserve everything between A segment and 1MB:
+	 *
+	 * 0xa0000 - 0xbffff: legacy VGA
+	 * 0xc0000 - 0xfffff: RAM
+	 */
+	mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
+	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
+	                      (0x100000 - 0xc0000) >> 10);
 #if CONFIG_CHROMEOS_RAMOOPS
-	mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+	reserved_ram_resource(dev, index++,
+			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
 			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
 #endif
 }
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 13390bd..c39933f 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -127,10 +127,14 @@ static void add_fixed_resources(struct device *dev, int index)
 		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 	}
 
-	mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
+	mmio_resource(dev, index++, legacy_hole_base_k,
+			(0xc0000 >> 10) - legacy_hole_base_k);
+	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+			(0x100000 - 0xc0000) >> 10);
 
 #if CONFIG_CHROMEOS_RAMOOPS
-	mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
+	reserved_ram_resource(dev, index++,
+			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
 			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
 #endif