[coreboot-gerrit] New patch to review for coreboot: c5293d3 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
Paul Menzel (paulepanter@users.sourceforge.net)
gerrit at coreboot.org
Fri Mar 29 15:52:47 CET 2013
Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2957
-gerrit
commit c5293d3b579f2b264513f622b375e1ac5a7b5d1d
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date: Fri Mar 29 15:39:54 2013 +0100
ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`
When building the ASRock E350M1, the following warning is shown.
$ make # on Jenkins (build server)
[…]
CC mainboard/asrock/e350m1/mainboard.ramstage.o
src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable':
src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration]
[…]
The warning was introduced by moving the initialization of the
ASF registers using `pm_iowrite` to `mainboard.c` in
commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3
Author: Jens Rottmann <JRottmann at LiPPERTembedded.de>
Date: Thu Mar 21 22:21:28 2013 +0100
Asrock E350M1: Use SPD read code from F14 wrapper
Reviewed-on: http://review.coreboot.org/2875
and is fixed by including `southbridge/amd/cimx/cimx_util.h`
declaring `pm_iowrite`.
Note, that the other AMD SB800 based boards seem to use the
header file `southbridge/amd/sb800/sb800.h` so no warning is shown
for those. Since the CIMx code is used, the routines from the
CIMx are more appropriote to declare these functions.
Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099
Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
src/mainboard/asrock/e350m1/mainboard.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index be5c36c..cdac2be 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -25,6 +25,7 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
//#include <southbridge/amd/sb800/sb800.h>
+#include <southbridge/amd/cimx/cimx_util.h>
//#define SMBUS_IO_BASE 0x6000
void set_pcie_reset(void);
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