[coreboot-gerrit] Patch merged into coreboot/master: e383442 x86: mtrr: add hole punching support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e383442943344f3a14b97e5625a8223f73cac5b0
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Mar 28 20:48:51 2013 -0500

    x86: mtrr: add hole punching support
    
    Some ranges would use less variable MTRRs if an UC area
    can be carved off the top of larger WB range. Implement this
    approach by doing 3 passes over each region in the addres space:
      1. UC default type. Cover non-UC and non-WB regions with respectie type.
         Punch UC hole at upper end of larger WB regions with WB type.
      2. UC default type. Cover non-UC regions with respective type.
      3. WB default type. Cover non-WB regions with respective type.
    The hole at upper end of a region uses the same min alignment of 64MiB.
    
    Below are results using a combination of options. The board this was
    tested on has 10 variable MTRRs at its disposal. It has 4GiB of RAM.
    
    IO hole config #1: hole starts at 0xad800000
    
    No CACHE_ROM or WRCOMB resources (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x0000000100000000 size 0x52800000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 4/9.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    No CACHE_ROM. 1 WRCOMB resource (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 6/10.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
    MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (taks 10 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
    0x00000000ad800000 - 0x00000000ff800000 size 0x52000000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6
    MTRR: default type WB/UC MTRR counts: 11/10.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x0000000080000000 mask 0x0000007fe0000000 type 6
    MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 6
    MTRR: 3 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
    MTRR: 4 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
    MTRR: 5 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 6 base 0x0000000100000000 mask 0x0000007fc0000000 type 6
    MTRR: 7 base 0x0000000140000000 mask 0x0000007ff0000000 type 6
    Taking a reserved OS MTRR.
    MTRR: 8 base 0x000000014f600000 mask 0x0000007fffe00000 type 0
    Taking a reserved OS MTRR.
    MTRR: 9 base 0x000000014f800000 mask 0x0000007fff800000 type 0
    
    A combination of CACHE_ROM and WRCOMB just won't work.
    
    IO hole config #2: hole starts at 0x80000000:
    
    No CACHE_ROM or WRCOMB resources (takes 1 MTRR):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x0000000100000000 size 0x80000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 1/5.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007f80000000 type 0
    
    No CACHE_ROM. 1 WRCOMB resource (takes 4 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 4/6.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0
    MTRR: 1 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
    MTRR: 2 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 3 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
    
    CACHE_ROM and no WRCOMB resources (takes 6 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000ff800000 size 0x7f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 9/6.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6
    MTRR: 3 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
    MTRR: 4 base 0x000000017d000000 mask 0x0000007fff000000 type 0
    MTRR: 5 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
    
    CACHE_ROM and 1 WRCOMB resource (takes 7 MTRRs):
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
    0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
    0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
    0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
    0x00000000e0000000 - 0x00000000ff800000 size 0x1f800000 type 0
    0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
    0x0000000100000000 - 0x000000017ce00000 size 0x7ce00000 type 6
    MTRR: default type WB/UC MTRR counts: 10/7.
    MTRR: UC selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
    MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
    MTRR: 2 base 0x00000000ff800000 mask 0x0000007fff800000 type 0
    MTRR: 3 base 0x0000000100000000 mask 0x0000007f80000000 type 6
    MTRR: 4 base 0x000000017ce00000 mask 0x0000007fffe00000 type 0
    MTRR: 5 base 0x000000017d000000 mask 0x0000007fff000000 type 0
    MTRR: 6 base 0x000000017e000000 mask 0x0000007ffe000000 type 0
    
    Change-Id: Iceb9b64991accf558caae2e7b0205951e9bcde44
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2925
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 29 15:44:04 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Mar 29 20:11:56 2013, giving +2
See http://review.coreboot.org/2925 for details.

-gerrit