[coreboot-gerrit] Patch set updated for coreboot: f7bc16e hardwaremain: drop boot_complete parameter

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3212

-gerrit

commit f7bc16e31aaba6a187fa453a501968ec13526163
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon May 6 16:49:56 2013 -0700

    hardwaremain: drop boot_complete parameter
    
    it has been unused since 9 years or so, hence drop it.
    
    Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/lib/c_start.S                        |  9 ---------
 src/include/bootstate.h                           |  2 +-
 src/lib/hardwaremain.c                            | 12 +++---------
 src/mainboard/emulation/qemu-armv7/ramstage.c     |  6 ++----
 src/mainboard/google/snow/ramstage.c              |  8 +++-----
 src/northbridge/via/vx800/examples/chipset_init.c |  2 +-
 6 files changed, 10 insertions(+), 29 deletions(-)

diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 32af0cc..99a4d92 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -49,12 +49,6 @@ _start:
 	pushl	$0
 	pushl	$0
 
-	/* push the boot_complete flag */
-	pushl	%ebp
-
-	/* Save the stack location */
-	movl	%esp, %ebp
-
 	/* Initialize the Interrupt Descriptor table */
 	leal	_idt, %edi
 	leal	vec0, %ebx
@@ -80,9 +74,6 @@ _start:
 	 */
 	post_code(POST_PRE_HARDWAREMAIN)	/* post fe */
 
-	/* Restore the stack location */
-	movl	%ebp, %esp
-
 #if CONFIG_GDB_WAIT
 	call gdb_stub_breakpoint
 #endif
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 0370c36..40822a7 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -165,7 +165,7 @@ void boot_state_current_block(void);
 void boot_state_current_unblock(void);
 
 /* Entry into the boot state machine. */
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
 
 /* In order to schedule boot state callbacks at compile-time specify the
  * entries in an array using the BOOT_STATE_INIT_ENTRIES and
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 13aa512..99b4a06 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -444,7 +444,7 @@ static void boot_state_schedule_static_entries(void)
 	}
 }
 
-void hardwaremain(int boot_complete)
+void hardwaremain(void)
 {
 	timestamp_stash(TS_START_RAMSTAGE);
 	post_code(POST_ENTRY_RAMSTAGE);
@@ -454,17 +454,11 @@ void hardwaremain(int boot_complete)
 
 	post_code(POST_CONSOLE_READY);
 
-	printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n",
-		      coreboot_version, coreboot_extra_version, coreboot_build,
-		      (boot_complete)?"rebooting":"booting");
+	printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n",
+		      coreboot_version, coreboot_extra_version, coreboot_build);
 
 	post_code(POST_CONSOLE_BOOT_MSG);
 
-	/* If we have already booted attempt a hard reboot */
-	if (boot_complete) {
-		hard_reset();
-	}
-
 	/* Schedule the static boot state entries. */
 	boot_state_schedule_static_entries();
 
diff --git a/src/mainboard/emulation/qemu-armv7/ramstage.c b/src/mainboard/emulation/qemu-armv7/ramstage.c
index 24d0d7f..5fce9fa 100644
--- a/src/mainboard/emulation/qemu-armv7/ramstage.c
+++ b/src/mainboard/emulation/qemu-armv7/ramstage.c
@@ -15,10 +15,8 @@
 
 #include <console/console.h>
 
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
 void main(void)
 {
-	console_init();
-	printk(BIOS_INFO, "hello from ramstage\n");
-	hardwaremain(0);
+	hardwaremain();
 }
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index 09b51a7..72f830d 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -77,12 +77,10 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
 }
 
 
-void hardwaremain(int boot_complete);
+void hardwaremain(void);
 void main(void)
 {
-	console_init();
-	printk(BIOS_INFO,
-	       "hello from ramstage; now with deluxe exception handling.\n");
+	/* FIXME this should be moved elsewhere. We don't want ramstage.c */
 
 	/* set up coreboot tables */
 	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
@@ -114,7 +112,7 @@ void main(void)
 
 	power_enable_xclkout();
 
-	hardwaremain(0);
+	hardwaremain();
 }
 
 /* TODO: transplanted DP stuff, clean up once we have something that works */
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 1e06d47..d9b85e4 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -604,7 +604,7 @@ void init_VIA_chipset(void)
  *	In the dev_enumerate() phase,
  */
 
-void hardwaremain(int boot_complete)
+void hardwaremain(void)
 {
 	struct lb_memory *lb_mem;
 #if CONFIG_HAVE_ACPI_RESUME