New patch to review for coreboot: baf59df AMD Family 10h–14h CPUs: AGESA: Provide monotonic counter

[Paul Menzel (paulepanter@users.sourceforge.net)]

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3264

-gerrit

commit baf59dff8899efbd953cae5790d6d8d231026f5a
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Mon May 13 23:36:02 2013 +0200

    AMD Family 10h–14h CPUs: AGESA: Provide monotonic counter
    
    Big thanks to Rudolf for educating me on accessing indexed registers [1].
    
    Unfortunately, the PCI access helpers seem to be not available in
    romstage.
    
    1. `arch/io.h` is changed to make it compile.
    2. Booting fails with `get_pbus: dev is NULL!` [2].
    
    The question is, if the CPU root complex can be accessed that early.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-May/075871.html
    [2] http://www.coreboot.org/pipermail/coreboot/2013-May/075874.html
    
    Change-Id: I7bd13512646c5defed536812087104e1491f228c
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/arch/x86/include/arch/io.h      |  2 ++
 src/cpu/amd/agesa/Kconfig           |  9 +++++-
 src/cpu/amd/agesa/Makefile.inc      |  2 ++
 src/cpu/amd/agesa/monotonic_timer.c | 64 +++++++++++++++++++++++++++++++++++++
 4 files changed, 76 insertions(+), 1 deletion(-)

diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 29c8339..a7c62e7 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -188,6 +188,7 @@ static inline int log2f(int value)
         return r;
 
 }
+#endif
 
 #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
         (((SEGBUS) & 0xFFF) << 20) | \
@@ -206,6 +207,7 @@ static inline int log2f(int value)
 
 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
 
+#if defined(__PRE_RAM__) || defined(__SMM__)
 typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
 
 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index c660470..39c9ebb 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -27,7 +27,6 @@ config CPU_AMD_AGESA
 	default n
 	select TSC_SYNC_LFENCE
 	select UDELAY_LAPIC
-	select LAPIC_MONOTONIC_TIMER
 
 if CPU_AMD_AGESA
 
@@ -50,6 +49,14 @@ config UDELAY_LAPIC_FIXED_FSB
 	int
 	default 200
 
+config MONOTONIC_TIMER_REG
+	def_bool y
+	select HAVE_MONOTONIC_TIMER
+	help
+	  Provide a monotonic timer using the 1 MHz BIOS Timer.
+
+	  Selecting this option means that the timer is enabled, that means, the clock rate in the BIOS Timer Control indexed register (D0F0xE4_x0130_80F1) is not 00h.
+
 source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index b5f39d6..69cfa15 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -24,4 +24,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
+ramstage-$(CONFIG_MONOTONIC_TIMER_REG) += monotonic_timer.c
+
 cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/monotonic_timer.c b/src/cpu/amd/agesa/monotonic_timer.c
new file mode 100644
index 0000000..4f96ed1
--- /dev/null
+++ b/src/cpu/amd/agesa/monotonic_timer.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <stdint.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <timer.h>
+
+static struct monotonic_counter {
+	int initialized;
+	struct mono_time time;
+	uint32_t last_value;
+} mono_counter;
+
+static inline uint32_t read_counter_msr(void)
+{
+	/* D0F0xE4_x0130_80F0 BIOS Timer
+	 *
+	 * This field increments once every microsecond when the timer is
+	 * enabled. The counter rolls over and continues counting when it
+	 * reaches FFFF_FFFFh. A write to this register causes the counter
+	 * to reset and begin counting from the value written. */
+	pci_write_config32(PCI_DEV(0, 0, 0), 0xe4, 0x013080F0);
+
+	return pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+}
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+	uint32_t current_tick;
+	uint32_t usecs_elapsed;
+
+	if (!mono_counter.initialized) {
+		mono_counter.last_value = read_counter_msr();
+		mono_counter.initialized = 1;
+	}
+
+	current_tick = read_counter_msr();
+	usecs_elapsed = current_tick - mono_counter.last_value;
+
+	/* Update current time and tick values only if a full tick occurred. */
+	if (usecs_elapsed) {
+		mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
+		mono_counter.last_value = current_tick;
+	}
+
+	/* Save result. */
+	*mt = mono_counter.time;
+}