[coreboot-gerrit] New patch to review for coreboot: b9f51fb northbridge/intel/i945: Add TSEG Enabling support.
Denis Carikli (GNUtoo@no-log.org)
gerrit at coreboot.org
Fri May 24 17:26:34 CEST 2013
Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3282
-gerrit
commit b9f51fb4306bc58ba5ccd409d1dc11772e8f9aca
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date: Thu May 23 23:36:08 2013 +0200
northbridge/intel/i945: Add TSEG Enabling support.
The resource part of that patch is based on the
following commit: e6c3b1d30d3fa88af6da6fcc115aa6cba3c55d1c
(haswell: include TSEG region in cacheable memory)
Change-Id: I11fb5cb4083850ab0b1dc7cca86a59760aafbd17
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
src/cpu/x86/smm/smmhandler_tseg.S | 27 +++++++++++++++++++++++
src/cpu/x86/smm/smmrelocate.S | 29 +++++++++++++++++++++++++
src/northbridge/intel/i945/Kconfig | 4 ++++
src/northbridge/intel/i945/Makefile.inc | 1 +
src/northbridge/intel/i945/northbridge.c | 13 ++++++++++-
src/northbridge/intel/i945/raminit.c | 34 +++++++++++++++++++++++++++++
src/northbridge/intel/i945/raminit.h | 9 ++++++++
src/northbridge/intel/i945/smi.c | 37 ++++++++++++++++++++++++++++++++
8 files changed, 153 insertions(+), 1 deletion(-)
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
index eb5d63c..ca6c792 100644
--- a/src/cpu/x86/smm/smmhandler_tseg.S
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -63,6 +63,7 @@
#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL
#include <northbridge/intel/haswell/haswell.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945
#else
#error "Northbridge must define TSEG_BAR."
#endif
@@ -82,7 +83,20 @@
* All the bad magic is not all that bad after all.
*/
smm_handler_start:
+#if CONFIG_NORTHBRIDGE_INTEL_I945
+ /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */
+ movl $0x8000009c, %eax
+ movw $0xcf8, %dx
+ outl %eax, %dx
+ movw $0xcfc, %dx
+ inl %dx, %eax
+
+ /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/
+ subl $(CONFIG_I915_UMA_SIZE), %eax
+ subl $(CONFIG_SMM_TSEG_SIZE), %eax
+#else
movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
+#endif
addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */
andl $~1, %edx /* Remove lock bit */
@@ -195,7 +209,20 @@ smm_prot_start:
call smi_handler
/* Release lock */
+#if CONFIG_NORTHBRIDGE_INTEL_I945
+ /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */
+ movl $0x8000009c, %eax
+ movw $0xcf8, %dx
+ outl %eax, %dx
+ movw $0xcfc, %dx
+ inl %dx, %eax
+
+ /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/
+ subl $(CONFIG_I915_UMA_SIZE), %eax
+ subl $(CONFIG_SMM_TSEG_SIZE), %eax
+#else
movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */
+#endif
movl (%eax), %ebx /* Save TSEG_BAR in %ebx */
andl $~1, %ebx /* Remove lock bit */
addl $(smm_lock), %ebx
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 16d4b9f..44954f65 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -48,6 +48,7 @@
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#elif CONFIG_NORTHBRIDGE_INTEL_I945
#else
#error "Northbridge must define TSEG_BAR."
#endif
@@ -148,7 +149,21 @@ smm_relocate:
shl $10, %edx
#if CONFIG_SMM_TSEG
+#if CONFIG_NORTHBRIDGE_INTEL_I945
+ /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */
+ movl $0x8000009c, %eax
+ movw $0xcf8, %dx
+ outl %eax, %dx
+ movw $0xcfc, %dx
+ inl %dx, %eax
+
+ /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/
+ subl $(CONFIG_I915_UMA_SIZE), %eax
+ subl $(CONFIG_SMM_TSEG_SIZE), %eax
+ movl %eax, %ecx
+#else
movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
+#endif
addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
andl $~1, %eax /* Remove lock bit */
#else
@@ -166,7 +181,21 @@ smm_relocate:
jnc skip_smrr
/* TSEG base */
+#if CONFIG_NORTHBRIDGE_INTEL_I945
+ /* tolud_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD); */
+ movl $0x8000009c, %eax
+ movw $0xcf8, %dx
+ outl %eax, %dx
+ movw $0xcfc, %dx
+ inl %dx, %eax
+
+ /* tseg_base = tolud - CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE*/
+ subl $(CONFIG_I915_UMA_SIZE), %eax
+ subl $(CONFIG_SMM_TSEG_SIZE), %eax
+ movl %eax, %ecx
+#else
movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */
+#endif
addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */
andl $~1, %eax /* Remove lock bit */
movl %eax, %ebx
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 98170d2..65db608 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -74,4 +74,8 @@ config MARK_GRAPHICS_MEM_WRCOMB
memory is set as write-combining cache type. This option
enables marking the graphics memory as write-combining.
+config I915_UMA_SIZE
+ hex
+ default 0x800000
+
endif
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 92a8849..6fea3e0 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -27,3 +27,4 @@ romstage-y += errata.c
romstage-y += debug.c
smm-y += udelay.c
+smm-y += smi.c
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 154b293..43a31c3 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -94,6 +94,9 @@ static void pci_domain_set_resources(device_t dev)
unsigned long long tomk, tomk_stolen;
uint64_t tseg_memory_base = 0, tseg_memory_size = 0;
unsigned long index = 3;
+#if CONFIG_SMM_TSEG
+ struct resource *resource;
+#endif
/* Can we find out how much memory we can use at most
* this way?
@@ -186,8 +189,16 @@ static void pci_domain_set_resources(device_t dev)
reserved_ram_resource(dev, index++, graphics_ram_resource_base >> 10,
graphics_ram_resource_size >> 10);
#endif
-}
+#if CONFIG_SMM_TSEG
+ resource = new_resource(dev, index++);
+ resource->base = tseg_memory_base;
+ resource->size = tseg_memory_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+#endif
+}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b1a0684..edd6b6a 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -3052,6 +3052,36 @@ static void sdram_setup_processor_side(void)
MCHBAR32(SLPCTL) |= (1 << 8);
}
+#if CONFIG_SMM_TSEG
+static void sdram_enable_tseg(void)
+{
+ u8 reg8;
+
+ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM);
+ reg8 |= (1 << 0); /* TSEG Enable */
+
+ switch(CONFIG_SMM_TSEG_SIZE){
+
+ case 0x100000:
+ reg8 &= ~((1<<2)|(1<<1));
+ break;
+ case 0x200000:
+ reg8 &= ~(1<<1);
+ reg8 |= (1<<2);
+ break;
+ case 0x800000:
+ reg8 |= (1<<2)|(1<<1);
+ break;
+ default:
+ /* it should not happen because we guard
+ * ainst that in the raminit.h header
+ */
+ printk(BIOS_ERR, "Invalid TSEG size!\n");
+ }
+ pci_write_config8(PCI_DEV(0, 0, 0), ESMRAM, reg8);
+}
+#endif
+
/**
* @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
*/
@@ -3180,6 +3210,10 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
/* Enable Periodic RCOMP */
sdram_enable_rcomp();
+#if CONFIG_SMM_TSEG
+ sdram_enable_tseg();
+#endif
+
/* Tell ICH7 that we're done */
reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
reg8 &= ~(1 << 7);
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 2d8ef9e..7f08af5 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -75,5 +75,14 @@ void udelay(u32 us);
#if CONFIG_DEBUG_RAM_SETUP
void sdram_dump_mchbar_registers(void);
+
+#if CONFIG_SMM_TSEG
+#if ! (CONFIG_SMM_TSEG_SIZE == 0x100000 || \
+ CONFIG_SMM_TSEG_SIZE == 0x200000 || \
+ CONFIG_SMM_TSEG_SIZE == 0x800000)
+#error Invalid TSEG size
+#endif
+#endif
+
#endif
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/i945/smi.c b/src/northbridge/intel/i945/smi.c
new file mode 100644
index 0000000..0993b12
--- /dev/null
+++ b/src/northbridge/intel/i945/smi.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2013 Denis 'GNUtoo' Carikli
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#include <types.h>
+#include <arch/io.h>
+#include <cpu/x86/smm.h>
+#include "i945.h"
+
+#if CONFIG_SMM_TSEG
+static u32 tseg_base = 0;
+u32 smi_get_tseg_base(void)
+{
+ if (!tseg_base)
+ tseg_base = pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) -
+ CONFIG_I915_UMA_SIZE - CONFIG_SMM_TSEG_SIZE;
+ return tseg_base;
+}
+#endif
+
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