[coreboot-gerrit] Patch set updated for coreboot: 8f8b40e Update SMM for FSP systems

Marc Jones (marc.jones@se-eng.com) gerrit at coreboot.org
Fri Nov 8 19:16:36 CET 2013


Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4019

-gerrit

commit 8f8b40eece81f67c6b39ece4a0a51b3efd535ac7
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Tue Oct 29 22:20:45 2013 -0600

    Update SMM for FSP systems
    
    Add the FSP northbridge and southbridge includes.
    
    Change-Id: I5c7f395dc033caa8d0bf0313382769595d77f2a5
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 src/cpu/x86/smm/smmhandler_tseg.S | 7 +++++++
 src/cpu/x86/smm/smmrelocate.S     | 8 ++++++++
 2 files changed, 15 insertions(+)

diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
index eb5d63c..0c8643c 100644
--- a/src/cpu/x86/smm/smmhandler_tseg.S
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -64,8 +64,15 @@
 #include <northbridge/intel/haswell/haswell.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #else
+#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
+#include <northbridge/intel/fsp_sandybridge/northbridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
 #error "Northbridge must define TSEG_BAR."
 #endif
+#endif
+
+
 
 /* initially SMM is some sort of real mode. Let gcc know
  * how to treat the SMM handler stub
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 16d4b9f..20efb37 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -37,6 +37,8 @@
 #include "../../../southbridge/intel/sch/sch.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
 #include "../../../southbridge/intel/bd82x6x/pch.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
+#include "../../../southbridge/intel/fsp_bd82x6x/pch.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
 #include "../../../southbridge/intel/i82801ix/i82801ix.h"
 #else
@@ -49,8 +51,14 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
 #else
+#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
+#include <northbridge/intel/fsp_sandybridge/northbridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
 #error "Northbridge must define TSEG_BAR."
 #endif
+#endif
+
 #include <cpu/x86/mtrr.h>
 
 #endif /* CONFIG_SMM_TSEG */



More information about the coreboot-gerrit mailing list