[coreboot-gerrit] New patch to review for coreboot: 9cb9ca1 Remove MRC variables from 2065x CAR init.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Thu Nov 14 19:36:29 CET 2013
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4080
-gerrit
commit 9cb9ca139e19c92f82e270b067570b43608a87f0
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Thu Nov 14 18:49:26 2013 +0100
Remove MRC variables from 2065x CAR init.
2065x boards don't use MRC. And the space in question isn't used either.
Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/cpu/intel/model_2065x/cache_as_ram.inc | 19 +------------------
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index ec7335e..7cce53b 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -27,11 +27,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-/* Cache 4GB - MRC_SIZE_KB for MRC */
-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define NoEvictMod_MSR 0x2e0
@@ -147,17 +142,6 @@ clear_mtrrs:
wrmsr
post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
- /* Enable caching for ram init code to run faster */
- movl $MTRRphysBase_MSR(2), %ecx
- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
post_code(0x28)
/* Enable cache. */
@@ -166,8 +150,7 @@ clear_mtrrs:
movl %eax, %cr0
/* Set up the stack pointer below MRC variable space. */
- movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
- CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4 - 4096), %eax
+ movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - 4), %eax
movl %eax, %esp
/* Restore the BIST result. */
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