[coreboot-gerrit] Patch set updated for coreboot: 68bc45c lynxpoint: Expose ACPI Device for LP GPIO controller

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4158

-gerrit

commit 68bc45c65baa0b8b76654d56049ad6f97a00e21c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon May 6 14:02:27 2013 -0700

    lynxpoint: Expose ACPI Device for LP GPIO controller
    
    In order to probe the gpio-lynxpoint kernel driver the
    LP GPIO controller needs to be exposed as a specific
    ACPI device.
    
    This also allows the resources to be exposed to the OS via
    this device instead of the catch-all LPC device.
    
    Ensure the driver loads at boot:
    gpiochip_find_base: found new base at 162
    gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00
    
    Also ensure the driver is visible in sysfs:
    $ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label
    INT33C7:00
    
    Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50215
---
 src/southbridge/intel/lynxpoint/acpi/lpc.asl      | 58 ++++-------------------
 src/southbridge/intel/lynxpoint/acpi/serialio.asl | 50 +++++++++++++++++++
 2 files changed, 60 insertions(+), 48 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index f9bf578..7e26926 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -199,60 +199,22 @@ Device (LPCB)
 			    0x1, 0xff)
 
 			// GPIO region may be 128 bytes or 4096 bytes
-			IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE,
-			    0x1, 0x00, GPR1)
-			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR2)
-			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR3)
-			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR4)
+			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1)
 		})
 
 		Method (_CRS, 0, NotSerialized)
 		{
-			CreateByteField (^RBUF, ^GPR1._LEN, R1LN)
-			CreateByteField (^RBUF, ^GPR2._LEN, R2LN)
-			CreateByteField (^RBUF, ^GPR3._LEN, R3LN)
-			CreateByteField (^RBUF, ^GPR4._LEN, R4LN)
+			// LynxPoint-LP GPIO resources are defined in the
+			// SerialIO GPIO device and LynxPoint-H GPIO resources
+			// are defined here.
+			If (LNot (\ISLP ())) {
+				CreateByteField (^RBUF, ^GPR1._LEN, R1LN)
+				CreateWordField (^RBUF, ^GPR1._MIN, R1MN)
+				CreateWordField (^RBUF, ^GPR1._MAX, R1MX)
 
-			CreateWordField (^RBUF, ^GPR1._MIN, R1MN)
-			CreateWordField (^RBUF, ^GPR2._MIN, R2MN)
-			CreateWordField (^RBUF, ^GPR3._MIN, R3MN)
-			CreateWordField (^RBUF, ^GPR4._MIN, R4MN)
-
-			CreateWordField (^RBUF, ^GPR1._MAX, R1MX)
-			CreateWordField (^RBUF, ^GPR2._MAX, R2MX)
-			CreateWordField (^RBUF, ^GPR3._MAX, R3MX)
-			CreateWordField (^RBUF, ^GPR4._MAX, R4MX)
-
-			// Update GPIO region for LynxPoint-LP
-			If (\ISLP ()) {
-				// LynxPoint-LP
-				Store (R1MN, Local0)
-
-				// Update GPIO bank 1
-				Store (Local0, R1MN)
-				Store (Local0, R1MX)
-				Store (0xff, R1LN)
-
-				// Update GPIO bank 2
-				Add (Local0, 0x100, Local0)
-				Store (Local0, R2MN)
-				Store (Local0, R2MX)
-				Store (0xff, R2LN)
-
-				// Update GPIO bank 3
-				Add (Local0, 0x100, Local0)
-				Store (Local0, R3MN)
-				Store (Local0, R3MN)
-				Store (0xff, R3LN)
-
-				// Update GPIO bank 4
-				Add (Local0, 0x100, Local0)
-				Store (Local0, R4MN)
-				Store (Local0, R4MN)
-				Store (0xff, R4LN)
-			} Else {
-				// LynxPoint-H
 				// Update GPIO region length
+				Store (DEFAULT_GPIOBASE, R1MN)
+				Store (DEFAULT_GPIOBASE, R1MX)
 				Store (DEFAULT_GPIOSIZE, R1LN)
 			}
 			Return (RBUF)
diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
index 6ea23c6..03f6974 100644
--- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl
@@ -468,3 +468,53 @@ Device (SDIO)
 		}
 	}
 }
+
+Device (GPIO)
+{
+	// GPIO Controller
+	Name (_HID, "INT33C7")
+	Name (_CID, "INT33C7")
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		DWordIo (ResourceProducer,
+			MinFixed,    // IsMinFixed
+			MaxFixed,    // IsMaxFixed
+			PosDecode,   // Decode
+			EntireRange, // ISARanges
+			0x00000000,  // AddressGranularity
+			0x00000000,  // AddressMinimum
+			0x00000000,  // AddressMaximum
+			0x00000000,  // AddressTranslation
+			0x00000000,  // RangeLength
+			,            // ResourceSourceIndex
+			,            // ResourceSource
+			BAR0)
+	})
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		If (\ISLP ()) {
+			CreateDwordField (^RBUF, ^BAR0._MIN, BMIN)
+			CreateDwordField (^RBUF, ^BAR0._MAX, BMAX)
+			CreateDwordField (^RBUF, ^BAR0._LEN, BLEN)
+
+			Store (DEFAULT_GPIOSIZE, BLEN)
+			Store (DEFAULT_GPIOBASE, BMIN)
+			Store (Subtract (Add (DEFAULT_GPIOBASE,
+					      DEFAULT_GPIOSIZE), 1), BMAX)
+		}
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		If (\ISLP ()) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}