[coreboot-gerrit] Patch set updated for coreboot: 95d11b4 haswell: Update GT PM register value

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Nov 20 01:51:18 CET 2013

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4166


commit 95d11b42fd4ffe357f400b0382b4c7f1ebc4c57d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri May 10 11:00:07 2013 -0700

    haswell: Update GT PM register value
    This was changed to 0x80000000 in SA BWG 1.5.0.
    Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/50852
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
 src/northbridge/intel/haswell/gma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index e577fb5..f3ddbd3 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -124,7 +124,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
 	gtt_write(0x12054, 0x0000000a);
 	gtt_write(0x22054, 0x0000000a);
-	gtt_write(0x0a008, 0x10000000);
+	gtt_write(0x0a008, 0x80000000);
 	gtt_write(0x0a024, 0x00000b92);
 	/* Enable RC6 in idle */

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