[coreboot-gerrit] New patch to review for coreboot: 4065d0c CBMEM intel: Define get_top_of_ram() once per chipset
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Oct 27 11:58:52 CET 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3993
-gerrit
commit 4065d0cfb95b23d1267867511389135114b47852
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Oct 15 17:19:41 2013 +0300
CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.
Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.
Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/northbridge/intel/haswell/Makefile.inc | 2 +
src/northbridge/intel/haswell/northbridge.c | 10 -----
src/northbridge/intel/haswell/ram_calc.c | 35 +++++++++++++++
src/northbridge/intel/haswell/raminit.c | 10 -----
src/northbridge/intel/i945/Makefile.inc | 2 +
src/northbridge/intel/i945/ram_calc.c | 57 +++++++++++++++++++++++++
src/northbridge/intel/i945/raminit.c | 33 --------------
src/northbridge/intel/sandybridge/Makefile.inc | 2 +
src/northbridge/intel/sandybridge/northbridge.c | 7 ---
src/northbridge/intel/sandybridge/ram_calc.c | 31 ++++++++++++++
src/northbridge/intel/sandybridge/raminit.c | 7 ---
11 files changed, 129 insertions(+), 67 deletions(-)
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index b2ac85e..5752a99 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -17,12 +17,14 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += mrccache.c
+romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += mrccache.c
romstage-y += early_init.c
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index ac61ca4..9440999 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -535,16 +535,6 @@ static void northbridge_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
-unsigned long get_top_of_ram(void)
-{
- u32 reg;
-
- /* The top the reserve regions fall just below the TSEG region. */
- reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
-
- return (reg & ~((1 << 20) - 1));
-}
-
static void northbridge_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
new file mode 100644
index 0000000..99e7d67
--- /dev/null
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include "haswell.h"
+
+unsigned long get_top_of_ram(void)
+{
+ /*
+ * Base of TSEG is top of usable DRAM below 4GiB. The register has
+ * 1 MiB alignement.
+ */
+ u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return (unsigned long) tom & ~((1 << 20) - 1);
+}
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index a90b360..171f738 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -201,13 +201,3 @@ void sdram_initialize(struct pei_data *pei_data)
report_memory_config();
}
-
-unsigned long get_top_of_ram(void)
-{
- /*
- * Base of TSEG is top of usable DRAM below 4GiB. The register has
- * 1 MiB alignement.
- */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom & ~((1 << 20) - 1);
-}
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 92a8849..67643eb 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -17,10 +17,12 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += errata.c
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
new file mode 100644
index 0000000..4ece540
--- /dev/null
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include "i945.h"
+
+unsigned long get_top_of_ram(void)
+{
+ u32 tom;
+
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
+ /* IGD enabled, get top of Memory from BSM register */
+ tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+ } else {
+ tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+ }
+
+ /* if TSEG enabled subtract size */
+ switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
+ case 0x01:
+ /* 1MB TSEG */
+ tom -= 0x10000;
+ break;
+ case 0x03:
+ /* 2MB TSEG */
+ tom -= 0x20000;
+ break;
+ case 0x05:
+ /* 8MB TSEG */
+ tom -= 0x80000;
+ break;
+ default:
+ /* TSEG either disabled or invalid */
+ break;
+ }
+ return (unsigned long) tom;
+}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b50f1d8..f4cba94 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -3184,36 +3184,3 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
sdram_setup_processor_side();
}
-
-unsigned long get_top_of_ram(void)
-{
- u32 tom;
-
- if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
- /* IGD enabled, get top of Memory from BSM register */
- tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
- } else {
- tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
- }
-
- /* if TSEG enabled subtract size */
- switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
- case 0x01:
- /* 1MB TSEG */
- tom -= 0x10000;
- break;
- case 0x03:
- /* 2MB TSEG */
- tom -= 0x20000;
- break;
- case 0x05:
- /* 8MB TSEG */
- tom -= 0x80000;
- break;
- default:
- /* TSEG either disabled or invalid */
- break;
- }
- return (unsigned long) tom;
-}
-
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index be07e93..2c2e05a 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -17,12 +17,14 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-y += mrccache.c
+romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += mrccache.c
romstage-y += early_init.c
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index a03b8a6..7db9301 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -51,13 +51,6 @@ int bridge_silicon_revision(void)
return bridge_revision_id;
}
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG);
- return (unsigned long) tom;
-}
-
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
new file mode 100644
index 0000000..3693a07
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include "sandybridge.h"
+
+unsigned long get_top_of_ram(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return (unsigned long) tom;
+}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3b321d7..6fca4a0 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -304,10 +304,3 @@ void sdram_initialize(struct pei_data *pei_data)
if (pei_data->boot_mode != 2)
save_mrc_data(pei_data);
}
-
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
-}
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