[coreboot-gerrit] Patch set updated for coreboot: e6374d0 Add get_cbmem_table for ARM

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Thu Sep 5 08:19:41 CEST 2013


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3560

-gerrit

commit e6374d02f9520bbb70e3260dec26bec26e4f9fe0
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 22 14:05:28 2013 +0300

    Add get_cbmem_table for ARM
    
    Follow-up will remove globals but there is circular dependency
    in patches. Patch "Use get_cbmem_toc in ramstage" will recover
    correct operation for these two boards.
    
    Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/arch/armv7/tables.c               |  7 +++++++
 src/include/cbmem.h                   |  1 -
 src/lib/cbmem.c                       |  4 +++-
 src/mainboard/google/pit/mainboard.c  | 15 +++++++++------
 src/mainboard/google/snow/mainboard.c | 15 +++++++++------
 5 files changed, 28 insertions(+), 14 deletions(-)

diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c
index 0fc7399..62e99e8 100644
--- a/src/arch/armv7/tables.c
+++ b/src/arch/armv7/tables.c
@@ -36,6 +36,13 @@
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
 
+void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size)
+{
+	printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n");
+	*base = 0;
+	*size = 0;
+}
+
 void cbmem_arch_init(void)
 {
 }
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 9638a03..1096ce5 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -140,7 +140,6 @@ void backup_top_of_ram(uint64_t ramtop);
 void set_cbmem_table(uint64_t base, uint64_t size);
 #endif
 
-void cbmem_init(u64 baseaddr, u64 size);
 int cbmem_reinit(u64 baseaddr);
 
 struct cbmem_entry *get_cbmem_toc(void);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 3f8f243..245c582 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -80,7 +80,8 @@ void set_cbmem_table(uint64_t base, uint64_t size)
  *  - suspend/resume backup memory
  */
 
-void cbmem_init(u64 baseaddr, u64 size)
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+static void cbmem_init(u64 baseaddr, u64 size)
 {
 	struct cbmem_entry *cbmem_toc;
 	cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
@@ -102,6 +103,7 @@ void cbmem_init(u64 baseaddr, u64 size)
 		.size	= size - CBMEM_TOC_RESERVED
 	};
 }
+#endif
 
 int cbmem_reinit(u64 baseaddr)
 {
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 54ea042..5c88be5 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -221,17 +221,20 @@ static void mainboard_init(device_t dev)
 	// gpio_info();
 }
 
+void get_cbmem_table(uint64_t *base, uint64_t *size)
+{
+	*base = CONFIG_SYS_SDRAM_BASE +
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	*size = CONFIG_COREBOOT_TABLES_SIZE;
+}
+
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = &mainboard_init;
 
 	/* set up coreboot tables */
-	/* FIXME: this should happen somewhere else */
-	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
-	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
-				CONFIG_COREBOOT_TABLES_SIZE;
-	cbmem_init(high_tables_base, high_tables_size);
+	cbmem_initialize();
 
 	/* set up dcache and MMU */
 	/* FIXME: this should happen via resource allocator */
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 5aedac9..8e6b7c8 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -262,17 +262,20 @@ static void mainboard_init(device_t dev)
 	// gpio_info();
 }
 
+void get_cbmem_table(uint64_t *base, uint64_t *size)
+{
+	*base = CONFIG_SYS_SDRAM_BASE +
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	*size = CONFIG_COREBOOT_TABLES_SIZE;
+}
+
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = &mainboard_init;
 
 	/* set up coreboot tables */
-	/* FIXME: this should happen somewhere else */
-	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
-	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
-				CONFIG_COREBOOT_TABLES_SIZE;
-	cbmem_init(high_tables_base, high_tables_size);
+	cbmem_initialize();
 
 	/* set up dcache and MMU */
 	/* FIXME: this should happen via resource allocator */



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