[coreboot-gerrit] Patch set updated for coreboot: 50b7d14 CBMEM: Backup top_of_ram instead of cbmem_toc
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Sep 6 15:03:10 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557
-gerrit
commit 50b7d1462523d660d1383cb55a0e6d60fbacda1b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Sep 4 13:26:11 2013 +0300
CBMEM: Backup top_of_ram instead of cbmem_toc
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.
TODO: Redesign these get_top_of_ram() functions from scratch.
Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/boot/cbmem.c | 6 ++++++
src/cpu/amd/agesa/s3_resume.c | 3 ++-
src/cpu/amd/car/post_cache_as_ram.c | 3 ++-
src/include/cbmem.h | 2 +-
src/lib/cbmem.c | 9 ---------
src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++--
src/southbridge/amd/agesa/hudson/hudson.c | 13 ++++++++-----
src/southbridge/amd/cimx/sb700/lpc.c | 4 ++--
src/southbridge/amd/cimx/sb800/cfg.c | 12 ++++++++----
src/southbridge/amd/sb700/early_setup.c | 8 +++++---
src/southbridge/amd/sb700/lpc.c | 4 ++--
src/southbridge/amd/sb800/early_setup.c | 8 +++++---
src/southbridge/via/k8t890/early_car.c | 9 +++++++--
src/southbridge/via/k8t890/host_ctrl.c | 9 ++-------
src/southbridge/via/k8t890/k8t890.h | 2 +-
15 files changed, 53 insertions(+), 43 deletions(-)
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 333ca55..991a3e6 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -40,12 +40,18 @@ void get_cbmem_table(uint64_t *base, uint64_t *size)
#endif
#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__)
+void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
+{
+ /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */
+}
+
/* This is for compatibility with old boards only. Any new chipset and board
* must implement get_top_of_ram() for both romstage and ramstage to support
* features like CAR_MIGRATION and CBMEM_CONSOLE.
*/
void set_top_of_ram(uint64_t ramtop)
{
+ backup_top_of_ram(ramtop);
cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
}
#endif
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 6ba9212..fcc1604 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -120,7 +120,8 @@ inline void *backup_resume(void)
* printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096));
*/
- cbmem_reinit((u64) high_ram_base);
+ if (!cbmem_reinit((u64)high_ram_base))
+ return NULL;
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
if (((u32) resume_backup_memory == 0)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 18c278e..d20c393 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -45,7 +45,8 @@ static inline void *backup_resume(void) {
print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base);
print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096));
- cbmem_reinit((u64)high_ram_base);
+ if (!cbmem_reinit((u64)high_ram_base))
+ return NULL;
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 4ee0b2e..bbdfe38 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -132,8 +132,8 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry);
#ifndef __PRE_RAM__
extern uint64_t high_tables_base, high_tables_size;
void set_top_of_ram(uint64_t ramtop);
+void backup_top_of_ram(uint64_t ramtop);
void cbmem_late_set_table(uint64_t base, uint64_t size);
-void set_cbmem_toc(struct cbmem_entry *);
int cbmem_base_check(void);
#endif
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 6db9cb5..5ee81ac 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -47,11 +47,6 @@ uint64_t high_tables_base = 0;
uint64_t high_tables_size = 0;
#endif
-void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x)
-{
- /* do nothing, this should be called by chipset to save TOC in NVRAM */
-}
-
static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s)
{
if (base && size && s) {
@@ -113,10 +108,6 @@ void cbmem_init(u64 baseaddr, u64 size)
for (;;) ;
}
- /* we don't need to call this in romstage, useful only from ramstage */
-#ifndef __PRE_RAM__
- set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr);
-#endif
memset(cbmem_toc, 0, CBMEM_TOC_RESERVED);
cbmem_toc[0] = (struct cbmem_entry) {
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a0319ab..96861c9 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
#endif
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index e4cbc07..dac0ede 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,9 +40,9 @@ int acpi_get_sleep_type(void)
}
#endif
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
/* printk(BIOS_DEBUG, "dword=%x\n", dword); */
for (i = 0; i<4; i++) {
@@ -132,19 +132,22 @@ void hudson_enable(device_t dev)
}
}
-struct cbmem_entry *get_cbmem_toc(void)
+#if CONFIG_HAVE_ACPI_RESUME
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
+ if (!acpi_is_wakeup_early())
+ return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
-
+#endif
struct chip_operations southbridge_amd_agesa_hudson_ops = {
CHIP_NAME("ATI HUDSON")
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index 826ac05..91d7d2f 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -27,9 +27,9 @@
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 90ad5a9..8520548 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -37,9 +37,9 @@ int acpi_get_sleep_type(void)
#endif
#ifndef __PRE_RAM__
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xf8, i; /* temp */
printk(BIOS_DEBUG, "dword=%x\n", dword);
for (i = 0; i<4; i++) {
@@ -51,18 +51,22 @@ void set_cbmem_toc(struct cbmem_entry *toc)
}
#endif
-struct cbmem_entry *get_cbmem_toc(void)
+#if CONFIG_HAVE_ACPI_RESUME
+unsigned long get_top_of_ram(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
+ if (acpi_get_sleep_type() != 3)
+ return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
+#endif
/**
* @brief South Bridge CIMx configuration
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index a16fc9f..ddba1a8 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -729,19 +729,21 @@ int acpi_is_wakeup_early(void)
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
return (((tmp & (7 << 10)) >> 10) == 3);
}
-#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
+ if (!acpi_is_wakeup_early())
+ return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
+#endif
#endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 23775b0..a175210 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -84,9 +84,9 @@ static void lpc_init(device_t dev)
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
}
-void set_cbmem_toc(struct cbmem_entry *toc)
+void backup_top_of_ram(uint64_t ramtop)
{
- u32 dword = (u32) toc;
+ u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;
for (i = 0; i<4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 4f0c98a..b3d16bf 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -673,19 +673,21 @@ static int acpi_is_wakeup_early(void)
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
return (((tmp & (7 << 10)) >> 10) == 3);
}
-#endif
-struct cbmem_entry *get_cbmem_toc(void)
+unsigned long get_top_of_ram(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
+ if (!acpi_is_wakeup_early())
+ return 0;
for (xi = 0; xi<4; xi++) {
outb(xnvram_pos, BIOSRAM_INDEX);
xdata &= ~(0xff << (xi * 8));
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
- return (struct cbmem_entry *) xdata;
+ return (unsigned long) xdata;
}
+#endif
#endif
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index 000a532..d7049ae 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -183,6 +183,11 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-struct cbmem_entry *get_cbmem_toc(void) {
- return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+#if CONFIG_HAVE_ACPI_RESUME
+unsigned long get_top_of_ram(void)
+{
+ if (!acpi_is_wakeup_early())
+ return 0;
+ return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
+#endif
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 151a228..74351bc 100644
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) {
pci_write_config8(dev, 0xa6, 0x83);
}
-#if 0
-struct cbmem_entry *get_cbmem_toc(void) {
- return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
-}
-#endif
-void set_cbmem_toc(struct cbmem_entry *toc) {
- outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
+void backup_top_of_ram(uint64_t ramtop) {
+ outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index f0d0fe0..7f83ffa 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -31,7 +31,7 @@
/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
#define K8T890_NVRAM_IO_BASE 0xf00
-#define K8T890_NVRAM_CBMEM_TOC 0xfc
+#define K8T890_NVRAM_TOP_OF_RAM 0xfc
#define K8T890_MMCONFIG_MBAR 0x61
#define K8T890_MULTIPLE_FN_EN 0x4f
More information about the coreboot-gerrit
mailing list