[coreboot-gerrit] New patch to review for coreboot: 103bcad AMD Hudson: Move the Unify the s3_resume_init_data to SB
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Sun Sep 22 05:27:37 CEST 2013
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3932
-gerrit
commit 103bcad196646ec128afe310a2b2a4f1822e1ff5
Author: Zheng Bao <fishbaozi at gmail.com>
Date: Sun Sep 22 11:00:25 2013 +0800
AMD Hudson: Move the Unify the s3_resume_init_data to SB
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also
changes the final configuration. We need to make sure the settings in FchParam
in resume stage are the same as they were in cold boot stage, otherwise the
board can not wake up more than once.
Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
src/mainboard/amd/olivehill/agesawrapper.c | 55 +------------
src/mainboard/amd/parmer/agesawrapper.c | 57 +-------------
src/mainboard/amd/thatcher/agesawrapper.c | 55 +------------
src/mainboard/asrock/imb-a180/agesawrapper.c | 55 +------------
src/mainboard/asus/f2a85-m/agesawrapper.c | 56 +-------------
src/southbridge/amd/agesa/hudson/Makefile.inc | 1 +
src/southbridge/amd/agesa/hudson/hudson.h | 3 +
src/southbridge/amd/agesa/hudson/resume.c | 107 ++++++++++++++++++++++++++
8 files changed, 118 insertions(+), 271 deletions(-)
diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
index 06405ad..61a360c 100644
--- a/src/mainboard/amd/olivehill/agesawrapper.c
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -43,6 +43,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include "hudson.h"
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -523,58 +524,6 @@ UINT32 agesawrapper_amdinitresume(VOID)
}
#ifndef __PRE_RAM__
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
- FchParams->Gpp.GppPhyPllPowerDown = TRUE;
- FchParams->Gpp.GppDynamicPowerSaving = TRUE;
- FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
- FchParams->Gpp.NewGppAlgorithm = TRUE;
- FchParams->Gpp.GppPortMinPollingTime = 40;
-
- FchParams->Spi.SpiSpeed = 2;
- FchParams->Ir.IrConfig = 3;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
- FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
- FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
- FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
- FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
- FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
- FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
-}
-
UINT32 agesawrapper_fchs3earlyrestore (VOID)
{
AGESA_STATUS status = AGESA_SUCCESS;
@@ -589,7 +538,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
@@ -657,7 +605,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
index c160106..2f3cec8 100644
--- a/src/mainboard/amd/parmer/agesawrapper.c
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -43,6 +43,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include "hudson.h"
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -523,58 +524,6 @@ UINT32 agesawrapper_amdinitresume(VOID)
}
#ifndef __PRE_RAM__
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
- FchParams->Gpp.GppPhyPllPowerDown = TRUE;
- FchParams->Gpp.GppDynamicPowerSaving = TRUE;
- FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
- FchParams->Gpp.NewGppAlgorithm = TRUE;
- FchParams->Gpp.GppPortMinPollingTime = 40;
-
- FchParams->Spi.SpiSpeed = 2;
- FchParams->Ir.IrConfig = 3;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
- FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
- FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
- FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
- FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
- FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
- FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
-}
-
UINT32 agesawrapper_fchs3earlyrestore (VOID)
{
AGESA_STATUS status = AGESA_SUCCESS;
@@ -589,7 +538,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
+ //FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
@@ -657,7 +606,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
+ //FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index 9480bdc..67edfdc 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -43,6 +43,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include "hudson.h"
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -523,58 +524,6 @@ UINT32 agesawrapper_amdinitresume(VOID)
}
#ifndef __PRE_RAM__
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
- FchParams->Gpp.GppPhyPllPowerDown = TRUE;
- FchParams->Gpp.GppDynamicPowerSaving = TRUE;
- FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
- FchParams->Gpp.NewGppAlgorithm = TRUE;
- FchParams->Gpp.GppPortMinPollingTime = 40;
-
- FchParams->Spi.SpiSpeed = 2;
- FchParams->Ir.IrConfig = 3;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
- FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
- FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
- FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
- FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
- FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
- FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
-}
-
UINT32 agesawrapper_fchs3earlyrestore (VOID)
{
AGESA_STATUS status = AGESA_SUCCESS;
@@ -589,7 +538,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
@@ -659,7 +607,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c
index 06405ad..61a360c 100644
--- a/src/mainboard/asrock/imb-a180/agesawrapper.c
+++ b/src/mainboard/asrock/imb-a180/agesawrapper.c
@@ -43,6 +43,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include "hudson.h"
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -523,58 +524,6 @@ UINT32 agesawrapper_amdinitresume(VOID)
}
#ifndef __PRE_RAM__
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
- FchParams->Gpp.GppPhyPllPowerDown = TRUE;
- FchParams->Gpp.GppDynamicPowerSaving = TRUE;
- FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
- FchParams->Gpp.NewGppAlgorithm = TRUE;
- FchParams->Gpp.GppPortMinPollingTime = 40;
-
- FchParams->Spi.SpiSpeed = 2;
- FchParams->Ir.IrConfig = 3;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
- FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
- FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
- FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
- FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
- FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
- FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
-}
-
UINT32 agesawrapper_fchs3earlyrestore (VOID)
{
AGESA_STATUS status = AGESA_SUCCESS;
@@ -589,7 +538,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
@@ -657,7 +605,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c
index 66b8d4f..e4dd014 100644
--- a/src/mainboard/asus/f2a85-m/agesawrapper.c
+++ b/src/mainboard/asus/f2a85-m/agesawrapper.c
@@ -43,6 +43,7 @@
#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include "hudson.h"
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
@@ -525,59 +526,6 @@ UINT32 agesawrapper_amdinitresume(VOID)
}
#ifndef __PRE_RAM__
-
-extern FCH_DATA_BLOCK InitEnvCfgDefault;
-STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
-{
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
- FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
- FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
- FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
- FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
- FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
- FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
- FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
- FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
- FchParams->Gpp.GppPhyPllPowerDown = TRUE;
- FchParams->Gpp.GppDynamicPowerSaving = TRUE;
- FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
- FchParams->Gpp.NewGppAlgorithm = TRUE;
- FchParams->Gpp.GppPortMinPollingTime = 40;
-
- FchParams->Spi.SpiSpeed = 2;
- FchParams->Ir.IrConfig = 3;
-
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
- FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
- FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
- FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
- FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
- FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
- FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
- FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
- FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
- FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
- FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
- FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
- FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
- FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
- FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
- FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase;
- FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
- FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
- FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
- FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
- FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
- FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
- FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
- FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
- FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
- FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
- FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
- FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
-}
-
UINT32 agesawrapper_fchs3earlyrestore (VOID)
{
AGESA_STATUS status = AGESA_SUCCESS;
@@ -592,7 +540,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
@@ -662,7 +609,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID)
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
- FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 44e030c..374da3c 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -17,6 +17,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 686dbb5..e8f80aa 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -21,6 +21,7 @@
#define HUDSON_H
#include <device/pci_ids.h>
+#include <device/device.h>
#include "chip.h"
/* Power management index/data registers */
@@ -69,6 +70,8 @@ int acpi_is_wakeup_early(void);
#else
void hudson_enable(device_t dev);
void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev);
+void s3_resume_init_data(void *FchParams);
+
#endif
#endif /* HUDSON_H */
diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c
new file mode 100644
index 0000000..c96bdd5
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/resume.c
@@ -0,0 +1,107 @@
+#include "FchPlatform.h"
+#include "Fch.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include "hudson.h"
+#include "AGESA.h"
+
+extern FCH_DATA_BLOCK InitEnvCfgDefault;
+extern FCH_INTERFACE FchInterfaceDefault;
+extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
+extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
+
+#define DUMP_FCH_SETTING 0
+
+void s3_resume_init_data(void *data)
+{
+ FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data;
+ AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader;
+
+ *FchParams = InitEnvCfgDefault;
+ FchParams->StdHeader = StdHeader;
+
+ FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable;
+ FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable;
+ FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed;
+ FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed;
+ FchParams->Spi.SpiMode = InitResetCfgDefault.Mode;
+ FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode;
+ FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite;
+ FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap;
+ FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll;
+ FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2;
+ FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode;
+ FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg;
+ FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread;
+ FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed;
+ FchParams->Gpp = InitResetCfgDefault.Gpp;
+ FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable;
+
+ FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
+ FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
+ FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
+ FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
+ FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
+ FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
+ FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
+ FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
+ FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
+
+ FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
+ FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
+ FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
+ FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
+ FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
+ FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
+ FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
+ FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
+ FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
+ FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
+ FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
+ FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
+ FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
+ FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
+ FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
+ FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+ FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
+ FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
+ FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
+ FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
+ FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
+ FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
+ FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
+ FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
+ FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
+ FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
+ FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
+
+ FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig;
+ FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController;
+ FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig;
+ FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2;
+ FchParams->Sata.SataClass = FchInterfaceDefault.SataClass;
+ FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable;
+ FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable;
+ FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode;
+ FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable;
+ FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable;
+ FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable;
+ FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable;
+ FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable;
+ FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable;
+ FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;
+ FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
+
+#if !CONFIG_HUDSON_XHCI_ENABLE
+ FchParams->Usb.Xhci0Enable = FALSE;
+#endif
+ FchParams->Usb.Xhci1Enable = FALSE;
+#if DUMP_FCH_SETTING
+ int i;
+
+ for (i=0; i<sizeof(FchParams); i++) {
+ printk(BIOS_DEBUG, " %02x", ((u8 *)FchParams)[i]);
+ if ((i % 16 ) == 15)
+ printk(BIOS_DEBUG, "\n");
+ }
+#endif
+}
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