[coreboot-gerrit] New patch to review for coreboot: fd40751 lenovo/t530: Possibly missing gpio writeout

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436

-gerrit

commit fd4075177d1899fbd4e5bafe9b33a3c0597d68ca
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Fri Aug 1 20:30:21 2014 +1000

    lenovo/t530: Possibly missing gpio writeout
    
    Include raw dump for the purpose of review:
    
    CPU: ID 0x306a9, Processor Type 0x0, Family 0x6, Model 0x3a, Stepping 0x9
    Northbridge: 8086:0154 (3rd generation (Ivy Bridge family) Core Processor)
    Southbridge: 8086:1e55 (QM77)
    
    ========== GPIO DIFFS ===========
    
    GPIOBASE = 0x0500 (IO)
    
    gpiobase+0x0000: 0x3962a5ff (GPIO_USE_SEL)
    gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
    gpiobase+0x0000: 0x80090400 (GPIO_USE_SEL) DIFF
    
    gpiobase+0x0004: 0x8ebf6aff (GP_IO_SEL)
    gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
    gpiobase+0x0004: 0x60400400 (GP_IO_SEL) DIFF
    
    gpiobase+0x000c: 0x66917ebb (GP_LVL)
    gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
    gpiobase+0x000c: 0x646f7fbb (GP_LVL) DIFF
    
    gpiobase+0x0018: 0x00000000 (GPO_BLINK)
    gpiobase+0x0018: 0x00040000 (GPO_BLINK) DEFAULT
    gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF
    
    gpiobase+0x002c: 0x00002002 (GPI_INV)
    gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
    gpiobase+0x002c: 0x00002002 (GPI_INV) DIFF
    
    gpiobase+0x0030: 0x02ff08fe (GPIO_USE_SEL2)
    gpiobase+0x0030: 0x020300fe (GPIO_USE_SEL2) DEFAULT
    gpiobase+0x0030: 0x00fc0800 (GPIO_USE_SEL2) DIFF
    
    gpiobase+0x0034: 0x1f47f7fd (GP_IO_SEL2)
    gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
    gpiobase+0x0034: 0x00100809 (GP_IO_SEL2) DIFF
    
    gpiobase+0x0038: 0xbfbeff43 (GP_LVL2)
    gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
    gpiobase+0x0038: 0x1b14ff44 (GP_LVL2) DIFF
    
    gpiobase+0x0040: 0x000000ff (GPIO_USE_SEL3)
    gpiobase+0x0040: 0x00000030 (GPIO_USE_SEL3) DEFAULT
    gpiobase+0x0040: 0x000000cf (GPIO_USE_SEL3) DIFF
    
    gpiobase+0x0044: 0x00000fff (GPIO_SEL3)
    gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
    gpiobase+0x0044: 0x0000000f (GPIO_SEL3) DIFF
    
    gpiobase+0x0048: 0x00000f4f (GPIO_LVL3)
    gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
    gpiobase+0x0048: 0x00000f8f (GPIO_LVL3) DIFF
    
    Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/lenovo/t530/romstage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 36df52d..1b8f484 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -185,6 +185,7 @@ void main(unsigned long bist)
 	outl(0x3962a5ff, DEFAULT_GPIOBASE);        // GPIO_USE_SEL
 	outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4);    // GP_IO_SEL
 	outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc);  // GP_LVL
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18); // GPO_BLINK
 	outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); // GPI_INV
 	outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); // GPIO_USE_SEL2
 	outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); // GP_IO_SEL2