[coreboot-gerrit] Patch set updated for coreboot: 6a5b153 baytrail: add abstraction for IOSF accesses

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Mon Aug 4 20:55:07 CEST 2014


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6491

-gerrit

commit 6a5b153137f451aa80f9aeb20627528023e33461
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Mon Aug 4 16:41:05 2014 +0200

    baytrail: add abstraction for IOSF accesses
    
    Change-Id: Icbb95aae7ed3b5b5ce02a11b4c058b5598f110c0
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/soc/intel/baytrail/baytrail/iosf.h |  18 +++++
 src/soc/intel/baytrail/iosf.c          | 127 +++++++++++++++++++++++++++++++++
 2 files changed, 145 insertions(+)

diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h
index e936072..b8b2e59 100644
--- a/src/soc/intel/baytrail/baytrail/iosf.h
+++ b/src/soc/intel/baytrail/baytrail/iosf.h
@@ -101,6 +101,24 @@ void iosf_porta2_write(int reg, uint32_t val);
 uint32_t iosf_ssus_read(int reg);
 void iosf_ssus_write(int reg, uint32_t val);
 
+uint32_t read_iosf(uint32_t port, uint32_t reg);
+void write_iosf(uint32_t port, uint32_t reg, uint32_t val);
+
+#ifndef __ROMCC__
+static inline void rmw_iosf(uint32_t port, uint32_t reg, uint32_t mask, uint32_t val)
+{
+	uint32_t tmp = read_iosf(port, reg);
+	tmp &= mask;
+	tmp |= val;
+	write_iosf(port, reg, tmp);
+}
+
+static inline void or_iosf(uint32_t port, uint32_t reg, uint32_t val)
+{
+	rmw_iosf(port, reg, ~0, val);
+}
+#endif
+
 /* IOSF ports. */
 #define IOSF_PORT_AUNIT		0x00 /* IO Arbiter unit */
 #define IOSF_PORT_SYSMEMC	0x01 /* System Memory Controller */
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 2b07e2b..63c4b6a 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -19,6 +19,7 @@
 
 #include <arch/io.h>
 #include <baytrail/iosf.h>
+#include <console/console.h>
 
 #if !defined(__PRE_RAM__)
 #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
@@ -285,3 +286,129 @@ void iosf_ssus_write(int reg, uint32_t val)
 {
 	return iosf_write_port(IOSF_WRITE(SSUS), reg, val);
 }
+
+uint32_t read_iosf(uint32_t port, uint32_t reg)
+{
+	switch (port) {
+	case IOSF_PORT_AUNIT:
+		return iosf_aunit_read(reg);
+	case IOSF_PORT_CPU_BUS:
+		return iosf_cpu_bus_read(reg);
+	case IOSF_PORT_BUNIT:
+		return iosf_bunit_read(reg);
+	case IOSF_PORT_DUNIT_CH0:
+		return iosf_dunit_ch0_read(reg);
+	case IOSF_PORT_PMC:
+		return iosf_punit_read(reg);
+	case IOSF_PORT_USBPHY:
+		return iosf_usbphy_read(reg);
+	case IOSF_PORT_SEC:
+		return iosf_sec_read(reg);
+	case IOSF_PORT_0x45:
+		return iosf_port45_read(reg);
+	case IOSF_PORT_0x46:
+		return iosf_port46_read(reg);
+	case IOSF_PORT_0x47:
+		return iosf_port47_read(reg);
+	case IOSF_PORT_SCORE:
+		return iosf_score_read(reg);
+	case IOSF_PORT_0x55:
+		return iosf_port55_read(reg);
+	case IOSF_PORT_0x58:
+		return iosf_port58_read(reg);
+	case IOSF_PORT_0x59:
+		return iosf_port59_read(reg);
+	case IOSF_PORT_0x5a:
+		return iosf_port5a_read(reg);
+	case IOSF_PORT_USHPHY:
+		return iosf_ushphy_read(reg);
+	case IOSF_PORT_SCC:
+		return iosf_scc_read(reg);
+	case IOSF_PORT_LPSS:
+		return iosf_lpss_read(reg);
+	case IOSF_PORT_0xa2:
+		return iosf_porta2_read(reg);
+	case IOSF_PORT_CCU:
+		return iosf_ccu_read(reg);
+	case IOSF_PORT_SSUS:
+		return iosf_ssus_read(reg);
+	default:
+		printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
+		       port);
+		break;
+	}
+	return 0;
+}
+
+void write_iosf(uint32_t port, uint32_t reg, uint32_t val)
+{
+	switch (port) {
+	case IOSF_PORT_AUNIT:
+		iosf_aunit_write(reg, val);
+		break;
+	case IOSF_PORT_CPU_BUS:
+		iosf_cpu_bus_write(reg, val);
+		break;
+	case IOSF_PORT_BUNIT:
+		iosf_bunit_write(reg, val);
+		break;
+	case IOSF_PORT_DUNIT_CH0:
+		iosf_dunit_write(reg, val);
+		break;
+	case IOSF_PORT_PMC:
+		iosf_punit_write(reg, val);
+		break;
+	case IOSF_PORT_USBPHY:
+		iosf_usbphy_write(reg, val);
+		break;
+	case IOSF_PORT_SEC:
+		iosf_sec_write(reg, val);
+		break;
+	case IOSF_PORT_0x45:
+		iosf_port45_write(reg, val);
+		break;
+	case IOSF_PORT_0x46:
+		iosf_port46_write(reg, val);
+		break;
+	case IOSF_PORT_0x47:
+		iosf_port47_write(reg, val);
+		break;
+	case IOSF_PORT_SCORE:
+		iosf_score_write(reg, val);
+		break;
+	case IOSF_PORT_0x55:
+		iosf_port55_write(reg, val);
+		break;
+	case IOSF_PORT_0x58:
+		iosf_port58_write(reg, val);
+		break;
+	case IOSF_PORT_0x59:
+		iosf_port59_write(reg, val);
+		break;
+	case IOSF_PORT_0x5a:
+		iosf_port5a_write(reg, val);
+		break;
+	case IOSF_PORT_USHPHY:
+		iosf_ushphy_write(reg, val);
+		break;
+	case IOSF_PORT_SCC:
+		iosf_scc_write(reg, val);
+		break;
+	case IOSF_PORT_LPSS:
+		iosf_lpss_write(reg, val);
+		break;
+	case IOSF_PORT_0xa2:
+		iosf_porta2_write(reg, val);
+		break;
+	case IOSF_PORT_CCU:
+		iosf_ccu_write(reg, val);
+		break;
+	case IOSF_PORT_SSUS:
+		iosf_ssus_write(reg, val);
+		break;
+	default:
+		printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
+		       port);
+		break;
+	}
+}



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