[coreboot-gerrit] New patch to review for coreboot: 11c53dc exynos5420: Fix mmc clock source.

[Isaac Christensen (isaac.christensen@se-eng.com)]

Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6504

-gerrit

commit 11c53dc4db8df6ee4255ecfab0e0c04f8c782def
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Thu Aug 22 23:56:35 2013 +0800

    exynos5420: Fix mmc clock source.
    
    The DWMMC controller internally divided clock by values in CLKSEL registers,
    so we must adjust MMC clock for that.
    
    Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f
    Signed-off-by: Hung-Te Lin <hungte at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/66657
    Commit-Queue: Ronald G. Minnich <rminnich at chromium.org>
    Reviewed-by: Ronald G. Minnich <rminnich at chromium.org>
    Tested-by: Ronald G. Minnich <rminnich at chromium.org>
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
 src/cpu/samsung/exynos5420/clock.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 7ecb717..8a8e589 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -333,16 +333,29 @@ int clock_set_dwmci(enum periph_id peripheral)
 {
 	/* Request MMC clock value to 52MHz. */
 	const unsigned long freq = 52000000;
-	unsigned long sclk, div;
+	unsigned long sdclkin, cclkin;
 	int device_index = (int)peripheral - (int)PERIPH_ID_SDMMC0;
 
 	ASSERT(device_index >= 0 && device_index < 4);
-	sclk = get_mmc_clk(device_index);
-	if (!sclk) {
+	sdclkin = get_mmc_clk(device_index);
+	if (!sdclkin) {
 		return -1;
 	}
-	div = CEIL_DIV(sclk, freq);
-	set_mmc_clk(device_index, div);
+
+	/* The SDCLKIN is divided insided controller by the DIVRATIO field in
+	 * CLKSEL register, so we must calculate clock value as
+	 *   cclk_in = SDCLKIN / (DIVRATIO + 1)
+	 * Currently the RIVRATIO must be 3 for MMC0 and MMC2 on Exynos5420
+	 * (and must be configured in payload).
+	 */
+	if (device_index == 0 || device_index == 2){
+		int divratio = 3;
+		sdclkin /= (divratio + 1);
+	}
+	printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin);
+
+	cclkin = CEIL_DIV(sdclkin, freq);
+	set_mmc_clk(device_index, cclkin);
 	return 0;
 }