[coreboot-gerrit] New patch to review for coreboot: fabc98e cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6549

-gerrit

commit fabc98e9701f479a8ac4093f8221b20dabe565f2
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Sat Aug 9 15:48:51 2014 +1000

    cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs
    
    Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/cpu/amd/geode_lx/cache_as_ram.inc | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index 45fd166..db95dee 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -189,24 +189,25 @@ DCacheSetupGood:
 	call	main
 done_cache_as_ram_main:
 
-        /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
-
-        push   %edi
-        mov    $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
-        push   %esi
-        mov    $(CONFIG_DCACHE_RAM_BASE),%edi
-        mov    %edi,%esi
-        cld
-        rep movsl %ds:(%esi),%es:(%edi)
-        pop    %esi
-        pop    %edi
+	/* We now run over the stack-in-cache,
+	 * copying it back to itself to invalidate the cache */
+
+	push   %edi
+	mov    $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
+	push   %esi
+	mov    $(CONFIG_DCACHE_RAM_BASE),%edi
+	mov    %edi,%esi
+	cld
+	rep movsl %ds:(%esi),%es:(%edi)
+	pop    %esi
+	pop    %edi
 
 	/* Clear the cache out to ram */
 	wbinvd
-        /* re-enable the cache */
-        movl    %cr0, %eax
-        xorl             $(CR0_CD + CR0_NW), %eax        /* clear  the CD and NW bits */
-        movl    %eax, %cr0
+	/* re-enable the cache */
+	movl    %cr0, %eax
+	xorl    $(CR0_CD + CR0_NW), %eax        /* clear  the CD and NW bits */
+	movl    %eax, %cr0
 
 __main:
 	post_code(POST_PREPARE_RAMSTAGE)
@@ -227,4 +228,3 @@ __main:
 	post_code(POST_DEAD_CODE)
 	hlt
 	jmp	.Lhlt
-