[coreboot-gerrit] Patch set updated for coreboot: 5800482 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Mon Dec 1 19:05:52 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7602
-gerrit
commit 580048213899e7a8829d44c3e0cc7e480706afb6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Fri Nov 21 17:40:37 2014 +0200
AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
Move LPC decode enable out of agesawrapper.c. It should not be on the
execution path of AP CPUs and function is not related to AGESA per se.
Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/amd/olivehill/agesawrapper.c | 7 -------
src/mainboard/amd/olivehill/romstage.c | 3 +++
src/mainboard/amd/parmer/agesawrapper.c | 7 -------
src/mainboard/amd/parmer/romstage.c | 3 +++
src/mainboard/amd/thatcher/agesawrapper.c | 7 -------
src/mainboard/amd/thatcher/romstage.c | 14 ++++++--------
src/mainboard/asrock/imb-a180/agesawrapper.c | 7 -------
src/mainboard/asrock/imb-a180/romstage.c | 4 ++++
src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 7 -------
src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 3 +++
src/mainboard/lenovo/g505s/agesawrapper.c | 7 -------
src/mainboard/lenovo/g505s/romstage.c | 3 +++
12 files changed, 22 insertions(+), 50 deletions(-)
diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
index 22522db..242aa27 100644
--- a/src/mainboard/amd/olivehill/agesawrapper.c
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 0a982b6..c7d9397 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -56,7 +56,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* For serial port option, plug-in card on LPC. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
post_code(0x31);
console_init();
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
index c457fa3..b4b39d0 100644
--- a/src/mainboard/amd/parmer/agesawrapper.c
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 886ca57..4ab4d76 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -48,7 +48,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* For serial port option, plug-in card on LPC. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
post_code(0x31);
console_init();
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index cc3c069..7425eac 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 0dee909..46bb452 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -45,20 +45,18 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- u8 byte;
- device_t dev;
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
hudson_lpc_port80();
- //__asm__ volatile ("1: jmp 1b");
- /* TODO: */
- dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
- byte = pci_read_config8(dev, 0x48);
- byte |= 3; /* 2e, 2f */
- pci_write_config8(dev, 0x48, byte);
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* For serial port. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
+ u8 byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
post_code(0x31);
lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c
index 62fc053..1412392 100644
--- a/src/mainboard/asrock/imb-a180/agesawrapper.c
+++ b/src/mainboard/asrock/imb-a180/agesawrapper.c
@@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 877d458..5fe9209 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -77,7 +77,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*addr32 = t32;
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* For serial port. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
+
post_code(0x31);
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
index 5de359e..1ceffa0 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
@@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 5ae2c68..852cb8c 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -44,7 +44,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* Set LPC decode enables. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
post_code(0x31);
console_init();
diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c
index 5de359e..1ceffa0 100644
--- a/src/mainboard/lenovo/g505s/agesawrapper.c
+++ b/src/mainboard/lenovo/g505s/agesawrapper.c
@@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/*
@@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void)
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
- /* For serial port */
- PciData = 0xFF03FFD5;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 5ae2c68..852cb8c 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -44,7 +44,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
post_code(0x30);
+ /* Set LPC decode enables. */
+ pci_write_config32(dev, 0x44, 0xff03ffd5);
post_code(0x31);
console_init();
More information about the coreboot-gerrit
mailing list