[coreboot-gerrit] Patch set updated for coreboot: 1a31a9e fsp_baytrail: Allow selection of USB controller by get_option
Martin Roth (gaumless@gmail.com)
gerrit at coreboot.org
Wed Dec 3 17:36:38 CET 2014
Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7633
-gerrit
commit 1a31a9e3241199d2cd7e981b3128ed7ce8b5c4e3
Author: Martin Roth <martin.roth at se-eng.com>
Date: Tue Dec 2 21:51:03 2014 -0700
fsp_baytrail: Allow selection of USB controller by get_option
It was requested to be able to update XHCI vs EHCI via get_option,
so I've added it here for minnow max. This could get moved to the
chipset_fsp_util.c file later, but I'm adding it here for now.
More checking needs to be added to this:
- Are both controllers enabled in devicetree? If not, we don't want
to allow the switch.
Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/mainboard/intel/minnowmax/cmos.layout | 6 +++++-
src/mainboard/intel/minnowmax/romstage.c | 11 +++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
index a668188..c7dc88d 100644
--- a/src/mainboard/intel/minnowmax/cmos.layout
+++ b/src/mainboard/intel/minnowmax/cmos.layout
@@ -85,7 +85,8 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
+411 2 e 8 use_xhci_over_ehci
+#413 3 r 0 unused
# MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -133,6 +134,9 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 EHCI
+8 1 XHCI
+8 2 Default
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
index af63cab..a144722 100644
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ b/src/mainboard/intel/minnowmax/romstage.c
@@ -21,6 +21,8 @@
#include <baytrail/romstage.h>
#include <drivers/intel/fsp/fsp_util.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include "chip.h"
/**
@@ -54,6 +56,7 @@ void late_mainboard_romstage_entry()
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
+ u8 use_xhci = UpdData->PcdEnableXhci;
/*
* Minnow Max Board : 1GB SKU uses 2Gb density memory
@@ -65,5 +68,13 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
UpdData->PcdMemoryParameters.DIMMDensity
+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
+ /* Update XHCI UPD value if required */
+ get_option(&use_xhci, "use_xhci_over_ehci");
+ if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
+ UpdData->PcdEnableXhci = use_xhci;
+ printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
+ UpdData->PcdEnableXhci?"Enabled":"Disabled");
+ }
+
return;
}
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