[coreboot-gerrit] New patch to review for coreboot: 44e5b6e libpayload: arm: Pass the coreboot table location to the payload.
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Fri Dec 5 20:58:36 CET 2014
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7655
-gerrit
commit 44e5b6ee51d1681a176113f7d01dfe8d1cc9638e
Author: Gabe Black <gabeblack at google.com>
Date: Sat Feb 8 06:30:49 2014 -0800
libpayload: arm: Pass the coreboot table location to the payload.
To find the coreboot tables, the payload has historically searched for their
signature in a predefined region of memory. This is a little clumsy on x86,
but it works because you can assume certain regions are RAM. Also, there are
areas which are set aside for the firmware by convention. On x86 there's a
forwarding entry which goes in one of those fairly small conventional areas
and which points to the CBMEM area at the end of memory.
On ARM there aren't areas like that, so we've left out the forwarding entry and
gone directly to CBMEM. RAM may not start at the beginning of the address space
or go to its end, and that means there isn't really anywhere fixed you can put
the coreboot tables. That's meant that libpayload has to be configured on a
per board basis to know where to look for CBMEM.
Now that we have boards that don't have fixed amounts of memory, the location
of the end of RAM isn't fixed even on a per board level which means even that
workaround will no longer cut it.
This change makes coreboot pass the location of the coreboot tables to
libpayload using r0, the first argument register. That means we'll be able to
find them no matter where CBMEM is, and we can get rid of the per board search
ranges.
We can extend this mechanism to x86 as well, but there may be more
complications and it's less necessary there. It would be a good thing to do
eventually though.
BUG=None
TEST=Built and booted on nyan. Changed the size of memory and saw that the
payload could still find the coreboot tables where before it couldn't. Built
for pit, snow, and big.
BRANCH=None
Original-Change-Id: I7218afd999da1662b0db8172fd8125670ceac471
Original-Signed-off-by: Gabe Black <gabeblack at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185572
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
Original-Tested-by: Gabe Black <gabeblack at chromium.org>
(cherry picked from commit ca88f39c21158b59abe3001f986207a292359cf5)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: Iab14e9502b6ce7a55f0a72e190fa582f89f11a1e
---
payloads/libpayload/arch/arm/Config.in | 8 --------
payloads/libpayload/arch/arm/coreboot.c | 25 ++++++++++---------------
payloads/libpayload/arch/arm/head.S | 8 +++++++-
src/arch/arm/boot.c | 10 ++++++++--
4 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/payloads/libpayload/arch/arm/Config.in b/payloads/libpayload/arch/arm/Config.in
index b2ee527..b1f2bb4 100644
--- a/payloads/libpayload/arch/arm/Config.in
+++ b/payloads/libpayload/arch/arm/Config.in
@@ -33,12 +33,4 @@ config ARCH_SPECIFIC_OPTIONS # dummy
def_bool y
select LITTLE_ENDIAN
-config COREBOOT_INFO_RANGE_BASE
- hex "Base of the range to search for the coreboot tables"
-
-config COREBOOT_INFO_RANGE_SIZE
- hex "Size of the range to search for the coreboot tables"
- default 0x4000000
-
-
endif
diff --git a/payloads/libpayload/arch/arm/coreboot.c b/payloads/libpayload/arch/arm/coreboot.c
index b91db32..c7f371e 100644
--- a/payloads/libpayload/arch/arm/coreboot.c
+++ b/payloads/libpayload/arch/arm/coreboot.c
@@ -32,6 +32,9 @@
#include <libpayload.h>
#include <coreboot_tables.h>
+/* This pointer gets set in head.S and is passed in from coreboot. */
+void *cb_header_ptr;
+
/*
* Some of this is x86 specific, and the rest of it is generic. Right now,
* since we only support x86, we'll avoid trying to make lots of infrastructure
@@ -169,22 +172,16 @@ static void cb_parse_string(unsigned char *ptr, char **info)
*info = (char *)((struct cb_string *)ptr)->string;
}
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, struct sysinfo_t *info)
{
- struct cb_header *header;
+ struct cb_header *header = addr;
unsigned char *ptr = addr;
void *forward;
int i;
- for (i = 0; i < len; i += 16, ptr += 16) {
- header = (struct cb_header *)ptr;
- if (!strncmp((const char *)header->signature, "LBIO", 4))
- break;
- }
-
- /* We walked the entire space and didn't find anything. */
- if (i >= len)
- return -1;
+ /* No signature found. */
+ if (strncmp((const char *)header->signature, "LBIO", 4))
+ return -1;
if (!header->table_bytes)
return 0;
@@ -209,7 +206,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
switch (rec->tag) {
case CB_TAG_FORWARD:
forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
- return cb_parse_header(forward, len, info);
+ return cb_parse_header(forward, info);
continue;
case CB_TAG_MEMORY:
cb_parse_memory(ptr, info);
@@ -304,9 +301,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
int get_coreboot_info(struct sysinfo_t *info)
{
- int ret = cb_parse_header(
- phys_to_virt(CONFIG_LP_COREBOOT_INFO_RANGE_BASE),
- CONFIG_LP_COREBOOT_INFO_RANGE_SIZE, info);
+ int ret = cb_parse_header(cb_header_ptr, info);
return (ret == 1) ? 0 : -1;
}
diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S
index 54fdb5d..c5c96ea 100644
--- a/payloads/libpayload/arch/arm/head.S
+++ b/payloads/libpayload/arch/arm/head.S
@@ -34,12 +34,16 @@
*/
ENTRY(_entry)
+ /* Save off the location of the coreboot tables */
+ ldr r1, 1f
+ str r0, [r1]
+
/* TODO: disable interrupts */
/* TODO: Clear BSS */
/* Setup new stack */
- ldr sp, 1f
+ ldr sp, 2f
/* TODO: Save old stack pointer and link register */
@@ -56,4 +60,6 @@ ENDPROC(_entry)
.align 4
1:
+.word cb_header_ptr
+2:
.word _stack
diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c
index d872a79..85b2cce 100644
--- a/src/arch/arm/boot.c
+++ b/src/arch/arm/boot.c
@@ -17,12 +17,18 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
+#include <arch/cache.h>
#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
#include <payload_loader.h>
void arch_payload_run(const struct payload *payload)
{
+ void (*doit)(void *) = payload->entry;
+ void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE);
+
printk(BIOS_SPEW, "entry = %p\n", payload->entry);
- stage_exit(payload->entry);
+ cache_sync_instructions();
+ doit(cb_tables);
}
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