[coreboot-gerrit] Patch set updated for coreboot: 6d2d681 acer/aoa150: Autogenerate a new port.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Fri Dec 5 23:52:43 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7572
-gerrit
commit 6d2d68122e5bf95a64bb50c010442b7605c0b85d
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Oct 18 22:23:50 2014 +0200
acer/aoa150: Autogenerate a new port.
Just running autoport. Several things need to be fixed, it's done in
subsequent commit for now but both should be squashed before merge.
Change-Id: I7b9e1ac5ce185d0db2c69edd36429061c4c14020
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/Kconfig | 3 +
src/mainboard/acer/Kconfig | 20 ++++
src/mainboard/acer/aoa150/Kconfig | 54 +++++++++++
src/mainboard/acer/aoa150/Makefile.inc | 2 +
src/mainboard/acer/aoa150/acpi/ec.asl | 0
src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl | 74 +++++++++++++++
src/mainboard/acer/aoa150/acpi/platform.asl | 12 +++
src/mainboard/acer/aoa150/acpi/superio.asl | 0
src/mainboard/acer/aoa150/acpi_tables.c | 8 ++
src/mainboard/acer/aoa150/board_info.txt | 1 +
src/mainboard/acer/aoa150/cstates.c | 8 ++
src/mainboard/acer/aoa150/devicetree.cb | 103 ++++++++++++++++++++
src/mainboard/acer/aoa150/dsdt.asl | 25 +++++
src/mainboard/acer/aoa150/early_southbridge.c | 116 +++++++++++++++++++++++
src/mainboard/acer/aoa150/hda_verb.c | 47 +++++++++
src/mainboard/acer/aoa150/mainboard.c | 50 ++++++++++
src/mainboard/acer/aoa150/romstage.c | 1 +
src/mainboard/acer/aoa150/smihandler.c | 75 +++++++++++++++
18 files changed, 599 insertions(+)
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 29b439c..a29fc19 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -8,6 +8,8 @@ config VENDOR_AAEON
bool "Aaeon"
config VENDOR_ABIT
bool "Abit"
+config VENDOR_ACER
+ bool "Acer"
config VENDOR_ADLINK
bool "ADLINK"
config VENDOR_ADVANSUS
@@ -152,6 +154,7 @@ endchoice
source "src/mainboard/a-trend/Kconfig"
source "src/mainboard/aaeon/Kconfig"
source "src/mainboard/abit/Kconfig"
+source "src/mainboard/acer/Kconfig"
source "src/mainboard/adlink/Kconfig"
source "src/mainboard/advansus/Kconfig"
source "src/mainboard/advantech/Kconfig"
diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig
new file mode 100644
index 0000000..bdaaa97
--- /dev/null
+++ b/src/mainboard/acer/Kconfig
@@ -0,0 +1,20 @@
+if VENDOR_ACER
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_ACER_AOA150
+ bool "Aspire One AOA150"
+ help
+ Consult wiki for details.
+
+
+endchoice
+
+source "src/mainboard/acer/aoa150/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Acer"
+
+endif # VENDOR_APPLE
diff --git a/src/mainboard/acer/aoa150/Kconfig b/src/mainboard/acer/aoa150/Kconfig
new file mode 100644
index 0000000..99a4bb3
--- /dev/null
+++ b/src/mainboard/acer/aoa150/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_ACER_AOA150
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select BOARD_ROMSIZE_KB_2048
+ select CHANNEL_XOR_RANDOMIZATION
+ select CPU_INTEL_SOCKET_441
+ select EARLY_CBMEM_INIT
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_MP_TABLE
+ select INTEL_EDID
+ select INTEL_INT15
+ select MAINBOARD_DO_EDID
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GM
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select VGA
+
+config MAINBOARD_DIR
+ string
+ default acer/aoa150
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "AOA150"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,27ae.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,27ae"
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config MAX_CPUS
+ int
+ default 2
+endif
diff --git a/src/mainboard/acer/aoa150/Makefile.inc b/src/mainboard/acer/aoa150/Makefile.inc
new file mode 100644
index 0000000..2f60428
--- /dev/null
+++ b/src/mainboard/acer/aoa150/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += early_southbridge.c
+ramstage-y += cstates.c
diff --git a/src/mainboard/acer/aoa150/acpi/ec.asl b/src/mainboard/acer/aoa150/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl b/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..5354901
--- /dev/null
+++ b/src/mainboard/acer/aoa150/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x15 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x17 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x14 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x16 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x15 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x14 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x17 },
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x12 },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x11 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x13 },
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x15 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x16 },
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 },
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x14 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x15 },
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+ })
+ } Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKH, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKH, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+ })
+}
diff --git a/src/mainboard/acer/aoa150/acpi/platform.asl b/src/mainboard/acer/aoa150/acpi/platform.asl
new file mode 100644
index 0000000..62795d1
--- /dev/null
+++ b/src/mainboard/acer/aoa150/acpi/platform.asl
@@ -0,0 +1,12 @@
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
+
+Scope(\_SB)
+{
+ Method(_INI, 0)
+ {
+ \GOS()
+ }
+}
diff --git a/src/mainboard/acer/aoa150/acpi/superio.asl b/src/mainboard/acer/aoa150/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/acer/aoa150/acpi_tables.c b/src/mainboard/acer/aoa150/acpi_tables.c
new file mode 100644
index 0000000..92ceaed
--- /dev/null
+++ b/src/mainboard/acer/aoa150/acpi_tables.c
@@ -0,0 +1,8 @@
+#include <stdint.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+}
diff --git a/src/mainboard/acer/aoa150/board_info.txt b/src/mainboard/acer/aoa150/board_info.txt
new file mode 100644
index 0000000..0aeac00
--- /dev/null
+++ b/src/mainboard/acer/aoa150/board_info.txt
@@ -0,0 +1 @@
+Category: desktop
\ No newline at end of file
diff --git a/src/mainboard/acer/aoa150/cstates.c b/src/mainboard/acer/aoa150/cstates.c
new file mode 100644
index 0000000..997623a
--- /dev/null
+++ b/src/mainboard/acer/aoa150/cstates.c
@@ -0,0 +1,8 @@
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <northbridge/intel/i945/i945.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/acer/aoa150/devicetree.cb b/src/mainboard/acer/aoa150/devicetree.cb
new file mode 100644
index 0000000..61fe7f1
--- /dev/null
+++ b/src/mainboard/acer/aoa150/devicetree.cb
@@ -0,0 +1,103 @@
+chip northbridge/intel/i945
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.ndid" = "3"
+ register "gpu_backlight" = "0x1280128"
+ register "gpu_hotplug" = "0x00000220"
+ register "gpu_lvds_is_dual_channel" = "0"
+ register "gpu_lvds_use_spread_spectrum_clock" = "1"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_441
+ device lapic 0x0 on
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/i82801gx # Southbridge, FIXME: set gpiX_routing, gpe0_en and alt_gp_smi_en for EC support
+ register "c3_latency" = "0x03e9"
+ register "c4onc3_enable" = "1"
+ register "docking_supported" = "0"
+ register "ide_enable_primary" = "0"
+ register "ide_enable_secondary" = "0"
+ register "p_cnt_throttling_supported" = "1"
+ register "sata_ahci" = "0x1"
+ register "sata_ports_implemented" = "0x5"
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x1025 0x015b
+ ioapic_irq 2 INTA 0x16
+ end
+ device pci 1c.0 on # PCIe Port #1
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
+ device pci 1c.1 on # PCIe Port #2
+ device pci 00.0 on # Unsupported PCI device 10ec:8136
+ subsystemid 0x1025 0x015b
+ end
+ end
+ device pci 1c.2 on # PCIe Port #3
+ device pci 00.0 on # Unsupported PCI device 168c:001c
+ subsystemid 0x105b 0xe008
+ end
+ end
+ device pci 1c.3 on # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB UHCI
+ subsystemid 0x1025 0x015b
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10
+ end
+ device pci 1d.1 on # USB UHCI
+ subsystemid 0x1025 0x015b
+ end
+ device pci 1d.2 on # USB UHCI
+ subsystemid 0x1025 0x015b
+ end
+ device pci 1d.3 on # USB UHCI
+ subsystemid 0x1025 0x015b
+ end
+ device pci 1d.7 on # USB EHCI
+ subsystemid 0x1025 0x015b
+ end
+ device pci 1e.0 on # PCI bridge
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x1025 0x015b
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10
+ end
+ device pci 1f.1 off # IDE Controller
+ end
+ device pci 1f.2 on # SATA Controller
+ subsystemid 0x1025 0x015b
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1025 0x015b
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x1025 0x015b
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.0 on # VGA VGA controller
+ subsystemid 0x1025 0x015b
+ end
+ device pci 02.1 on # Display controller display controller
+ subsystemid 0x1025 0x015b
+ end
+ end
+end
diff --git a/src/mainboard/acer/aoa150/dsdt.asl b/src/mainboard/acer/aoa150/dsdt.asl
new file mode 100644
index 0000000..dc477d9
--- /dev/null
+++ b/src/mainboard/acer/aoa150/dsdt.asl
@@ -0,0 +1,25 @@
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include <cpu/intel/model_6dx/acpi/cpu.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <southbridge/intel/i82801gx/acpi/platform.asl>
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+}
diff --git a/src/mainboard/acer/aoa150/early_southbridge.c b/src/mainboard/acer/aoa150/early_southbridge.c
new file mode 100644
index 0000000..6eda5b8
--- /dev/null
+++ b/src/mainboard/acer/aoa150/early_southbridge.c
@@ -0,0 +1,116 @@
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+
+/* FIXME: hardcoded. */
+void mainboard_get_spd(spd_raw_data *spd)
+{
+ read_spd(&spd[0], 0x50);
+ read_spd(&spd[1], 0x51);
+ read_spd(&spd[2], 0x52);
+ read_spd(&spd[3], 0x53);
+}
+
+void setup_ich7_gpios(void)
+{
+ printk(BIOS_DEBUG, " GPIOS...");
+
+ outl(0x7f6af7fe, DEFAULT_GPIOBASE + GPIO_USE_SEL);
+ outl(0x8280ff81, DEFAULT_GPIOBASE + GP_IO_SEL);
+ outl(0x8080ffc1, DEFAULT_GPIOBASE + GP_LVL);
+ outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
+ outl(0x00000780, DEFAULT_GPIOBASE + GPI_INV);
+ outl(0x000100ce, DEFAULT_GPIOBASE + GPIO_USE_SEL2);
+ outl(0x00000038, DEFAULT_GPIOBASE + GP_IO_SEL2);
+ outl(0x000000c8, DEFAULT_GPIOBASE + GP_LVL2);
+}
+
+void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+
+ // Enable address decodes
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f03);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0069);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x0004);
+}
+
+void rcba_config(void)
+{
+ /* V0CTL Virtual Channel 0 Resource Control */
+ RCBA32(0x0014) = 0x80000001;
+ /* V1CAP Virtual Channel 1 Resource Capability */
+ RCBA32(0x001c) = 0x03128010;
+
+ /* Disable devices. */
+ RCBA32(0x3418) = 0x00300063;
+
+ /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
+ RCBA32(0x1e9c) = 0x000200f0;
+ RCBA32(0x1e98) = 0x000c0801;
+}
+void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
diff --git a/src/mainboard/acer/aoa150/hda_verb.c b/src/mainboard/acer/aoa150/hda_verb.c
new file mode 100644
index 0000000..62cf56b
--- /dev/null
+++ b/src/mainboard/acer/aoa150/hda_verb.c
@@ -0,0 +1,47 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0268, /* Codec Vendor / Device ID: Realtek */
+ 0x1025015b, /* Subsystem ID */
+
+ 0x0000000c, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x1025015b),
+
+ /* NID 0x12: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920),
+
+ /* NID 0x13: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x13, 0x411111f0),
+
+ /* NID 0x14: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x99130110),
+
+ /* NID 0x15: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x0321401f),
+
+ /* NID 0x16: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
+
+ /* NID 0x18: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a19830),
+
+ /* NID 0x19: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* NID 0x1a: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+ /* NID 0x1c: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
+
+ /* NID 0x1d: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4015812d),
+
+ /* NID 0x1e: Subsystem ID. */
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/acer/aoa150/mainboard.c b/src/mainboard/acer/aoa150/mainboard.c
new file mode 100644
index 0000000..1506bc8
--- /dev/null
+++ b/src/mainboard/acer/aoa150/mainboard.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/x86/include/arch/acpigen.h>
+#include <smbios.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_init(device_t dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, INT15_5F35_CL_DISPLAY_DEFAULT, 3);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/acer/aoa150/romstage.c b/src/mainboard/acer/aoa150/romstage.c
new file mode 100644
index 0000000..f1839f0
--- /dev/null
+++ b/src/mainboard/acer/aoa150/romstage.c
@@ -0,0 +1 @@
+/* dummy file */
diff --git a/src/mainboard/acer/aoa150/smihandler.c b/src/mainboard/acer/aoa150/smihandler.c
new file mode 100644
index 0000000..3cd7873
--- /dev/null
+++ b/src/mainboard/acer/aoa150/smihandler.c
@@ -0,0 +1,75 @@
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+ if (!pmbase)
+ return 0;
+
+ switch(data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* FIXME: EC support */
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* FIXME: EC support */
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
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