[coreboot-gerrit] Patch set updated for coreboot: 3004b7e i945: Consolidate interrupt routing.
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Fri Dec 5 23:52:51 CET 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7107
-gerrit
commit 3004b7e51e2232f93f93c34aacbd874769e8a80c
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Sat Nov 22 20:46:20 2014 +0100
i945: Consolidate interrupt routing.
The old code tried to make routing per-board, presumably for optimizing
IRQ balancing but instead failed at providing an error-free default.
Rewrite in unified and simplified way at the cost of minor performance hit
on very old OS.
Change-Id: I1ccc8949844ddcf18ebf81781c1aa1701058b378
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
.../apple/macbook21/acpi/i945_pci_irqs.asl | 71 -----------
src/mainboard/apple/macbook21/devicetree.cb | 37 ++++--
src/mainboard/apple/macbook21/mptable.c | 76 ------------
src/mainboard/apple/macbook21/romstage.c | 19 ---
src/mainboard/getac/p470/acpi/i945_pci_irqs.asl | 87 --------------
src/mainboard/getac/p470/devicetree.cb | 45 ++++---
src/mainboard/getac/p470/mptable.c | 85 -------------
src/mainboard/getac/p470/romstage.c | 15 ---
src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl | 85 -------------
src/mainboard/ibase/mb899/devicetree.cb | 45 ++++---
src/mainboard/ibase/mb899/mptable.c | 133 ---------------------
src/mainboard/ibase/mb899/romstage.c | 15 ---
.../intel/d945gclf/acpi/i945_pci_irqs.asl | 85 -------------
src/mainboard/intel/d945gclf/devicetree.cb | 43 ++++---
src/mainboard/intel/d945gclf/mptable.c | 90 --------------
src/mainboard/intel/d945gclf/romstage.c | 15 ---
.../kontron/986lcd-m/acpi/i945_pci_irqs.asl | 85 -------------
src/mainboard/kontron/986lcd-m/devicetree.cb | 43 ++++---
src/mainboard/kontron/986lcd-m/mptable.c | 116 ------------------
src/mainboard/kontron/986lcd-m/romstage.c | 15 ---
src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl | 63 ----------
src/mainboard/lenovo/t60/devicetree.cb | 43 ++++---
src/mainboard/lenovo/t60/mptable.c | 76 ------------
src/mainboard/lenovo/t60/romstage.c | 19 ---
src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl | 63 ----------
src/mainboard/lenovo/x60/devicetree.cb | 37 ++++--
src/mainboard/lenovo/x60/mptable.c | 78 ------------
src/mainboard/lenovo/x60/romstage.c | 19 ---
src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl | 84 -------------
src/mainboard/roda/rk886ex/devicetree.cb | 41 ++++---
src/mainboard/roda/rk886ex/mptable.c | 85 -------------
src/mainboard/roda/rk886ex/romstage.c | 15 ---
src/northbridge/intel/i945/acpi/hostbridge.asl | 3 -
src/northbridge/intel/i945/early_init.c | 23 ++++
src/northbridge/intel/i945/i945.h | 1 +
src/southbridge/intel/i82801gx/acpi/ich7.asl | 2 +
src/southbridge/intel/i82801gx/acpi/irq.asl | 82 +++++++++++++
src/southbridge/intel/i82801gx/chip.h | 12 --
src/southbridge/intel/i82801gx/lpc.c | 43 +++----
39 files changed, 348 insertions(+), 1646 deletions(-)
diff --git a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl b/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 6047def..0000000
--- a/src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0001FFFF, 0, 0, 0x10 },
- Package() { 0x0002FFFF, 0, 0, 0x10 },
- Package() { 0x0007FFFF, 0, 0, 0x10 },
- Package() { 0x001BFFFF, 0, 0, 0x16 },
- Package() { 0x001CFFFF, 0, 0, 0x11 },
- Package() { 0x001CFFFF, 1, 0, 0x10 },
- Package() { 0x001CFFFF, 2, 0, 0x12 },
- Package() { 0x001CFFFF, 3, 0, 0x13 },
- Package() { 0x001DFFFF, 0, 0, 0x15 },
- Package() { 0x001DFFFF, 1, 0, 0x13 },
- Package() { 0x001DFFFF, 2, 0, 0x12 },
- Package() { 0x001DFFFF, 3, 0, 0x10 },
- Package() { 0x001EFFFF, 0, 0, 0x16 },
- Package() { 0x001EFFFF, 1, 0, 0x14 },
- Package() { 0x001FFFFF, 0, 0, 0x12 },
- Package() { 0x001FFFFF, 1, 0, 0x13 },
- Package() { 0x001FFFFF, 3, 0, 0x10 }
- })
- } Else {
- Return (Package() {
- Package() { 0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0007FFFF, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001BFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001CFFFF, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001CFFFF, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001CFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001CFFFF, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001DFFFF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001DFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001DFFFF, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001DFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001EFFFF, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001EFFFF, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- Package() { 0x001FFFFF, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001FFFFF, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001FFFFF, 3, \_SB.PCI0.LPCB.LNKA, 0 }
- })
- }
-}
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index 8ca84f8..822d7a3 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -37,22 +37,21 @@ chip northbridge/intel/i945
device pci 00.0 on # Host bridge
subsystemid 0x8086 0x7270
end
- device pci 02.0 on # VGA controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # VGA controller
subsystemid 0x8086 0x7270
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -75,11 +74,20 @@ chip northbridge/intel/i945
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
+ ioapic_irq 2 INTA 0x16
subsystemid 0x8384 0x7680
end
- device pci 1c.0 on end # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # Ethernet
device pci 1c.1 on end # Atheros WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x8086 0x7270
end
device pci 1d.1 on # USB UHCI
@@ -94,7 +102,10 @@ chip northbridge/intel/i945
device pci 1d.7 on # USB2 EHCI
subsystemid 0x8086 0x7270
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x8086 0x7270
end
device pci 1f.1 on # IDE
diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c
deleted file mode 100644
index cc97e52..0000000
--- a/src/mainboard/apple/macbook21/mptable.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x16); /* HD Audio 0:1b.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x11); /* PCIe 0:1c.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x15); /* USB 0:1d.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x13); /* USB 0:1d.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x10); /* USB 0:1d.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x12); /* LPC 0:1f.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x13); /* IDE 0:1f.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x03, 0x02, 0x10); /* SATA 0:1f.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x03, (0x03 << 2) , 0x02, 0x13); /* Firewire 3:03.0 */
-
- mptable_lintsrc(mc, isa_bus);
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 443fdc5..3bbb07a 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -197,25 +197,6 @@ static void rcba_config(void)
/* V1CAP Virtual Channel 1 Resource Capability */
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- RCBA32(0x3108) = 0x10004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00214321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000001;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0235;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl b/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 7cd7401..0000000
--- a/src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // Network
- Package() { 0x0007ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 22 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 3, 0, 16 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Network 0:7.0
- Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
- })
- }
-}
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index ddcd749..919e9e3 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -31,19 +31,19 @@ chip northbridge/intel/i945
device pci 00.0 on end # host bridge
# autodetect:
#device pci 01.0 off end # i945 PCIe root port
- #device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10
+ end # vga controller
#device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0a"
- register "pirqb_routing" = "0x0a"
- register "pirqc_routing" = "0x0a"
- register "pirqd_routing" = "0x0a"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x0a"
- register "pirqh_routing" = "0x0a"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -64,26 +64,43 @@ chip northbridge/intel/i945
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe port 1
+ device pci 1b.0 on # High Definition Audio
+ ioapic_irq 2 INTA 0x16
+ end
+
+ device pci 1c.0 on # PCIe port 1
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13
+ end
device pci 1c.1 on end # PCIe port 2
device pci 1c.2 on end # PCIe port 3
device pci 1c.3 on end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14
chip southbridge/ti/pcixx12
end
end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/fdc37n972
device pnp 2e.0 off # Floppy
end
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
deleted file mode 100644
index 9b59bb4..0000000
--- a/src/mainboard/getac/p470/mptable.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
-
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index b57e6b7..32323bc 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -176,21 +176,6 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl b/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 142cb80..0000000
--- a/src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- //Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 17 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19},
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index a26d7c2..ccf6405 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -8,19 +8,19 @@ chip northbridge/intel/i945
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10
+ end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x07"
- register "pirqc_routing" = "0x05"
- register "pirqd_routing" = "0x07"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x06"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -35,22 +35,37 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- #device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16
+ end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/winbond/w83627ehg
device pnp 4e.0 off end # Floppy
device pnp 4e.1 off end # Parport
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
deleted file mode 100644
index 1baf728..0000000
--- a/src/mainboard/ibase/mb899/mptable.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct device *riser = NULL, *firewire = NULL;
- int firewire_bus = 0, riser_bus = 0, isa_bus;
- int ioapic_id;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- firewire = dev_find_device(0x104c, 0x8023, 0);
- if (firewire) {
- firewire_bus = firewire->bus->secondary;
- printk(BIOS_SPEW, "Firewire device is on bus %x\n",
- firewire_bus);
- }
-
- // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
- // highest bus number on the pci bus.
- riser = dev_find_device(0x3388, 0x0021, 0);
- if (!riser)
- riser = dev_find_device(0x3388, 0x0022, 0);
- if (riser) {
- riser_bus = riser->link_list->secondary;
- printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
- }
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
-
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x1, ioapic_id, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xc, ioapic_id, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xd, ioapic_id, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xe, ioapic_id, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xf, ioapic_id, 0xf);
-
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
-
- /* Internal PCI bus (Firewire, PCI slot) */
- if (firewire) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
- }
-
- if (riser) {
- /* Old riser card */
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
-
- /* New Riser Card */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
- }
-
- /* PCIe slot */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 1);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index ece65d8..6f3e943 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -148,21 +148,6 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
diff --git a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl b/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
deleted file mode 100644
index aa85527..0000000
--- a/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 22 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 2a3172b..9f9afff 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -29,19 +29,18 @@ chip northbridge/intel/i945
subsystemid 0x8086 0x464c inherit
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x07"
- register "pirqc_routing" = "0x05"
- register "pirqd_routing" = "0x07"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x06"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -56,22 +55,36 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/lpc47m15x
device pnp 2e.0 off # Floppy
end
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
deleted file mode 100644
index b0360bf..0000000
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
-
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
-
- /* Old riser card */
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
-
- /* New Riser Card */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x30, 0x2, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x34, 0x2, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x38, 0x2, 0x16);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 4194a80..f8fc155 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -74,21 +74,6 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x0146;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x0146;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl b/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
deleted file mode 100644
index cd1fed5..0000000
--- a/src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- Package() { 0x0001ffff, 1, 0, 17 },
- Package() { 0x0001ffff, 2, 0, 18 },
- Package() { 0x0001ffff, 3, 0, 19 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 16 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 16 },
- Package() { 0x001cffff, 1, 0, 17 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 17 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19},
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97/IDE 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- })
- }
-}
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index 6a5b221..1fdd4e5 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -9,19 +9,19 @@ chip northbridge/intel/i945
device domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on # vga controller
+ ioapic_irq 2 INTA 0x10
+ end
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -35,22 +35,37 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16
+ end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10
chip superio/winbond/w83627thg
device pnp 2e.0 off # Floppy
end
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
deleted file mode 100644
index 03f7370..0000000
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- struct device *riser = NULL, *firewire = NULL;
- int firewire_bus = 0, riser_bus = 0, isa_bus;
- int ioapic_id;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- firewire = dev_find_device(0x104c, 0x8023, 0);
- if (firewire) {
- firewire_bus = firewire->bus->secondary;
- }
-
- // If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
- // highest bus number on the pci bus.
- riser = dev_find_device(0x3388, 0x0021, 0);
- if (!riser)
- riser = dev_find_device(0x3388, 0x0022, 0);
- if (riser) {
- riser_bus = riser->link_list->secondary;
- }
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- ioapic_id = 2;
- smp_write_ioapic(mc, ioapic_id, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
-
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, ioapic_id, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, ioapic_id, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, ioapic_id, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, ioapic_id, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, ioapic_id, 0x11);
-
- /* Internal PCI bus (Firewire, PCI slot) */
- if (firewire) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x0, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, firewire_bus, 0x4, ioapic_id, 0x14);
- }
-
- if (riser) {
- /* Old riser card */
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
-
- /* New Riser Card */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x30, ioapic_id, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x34, ioapic_id, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x38, ioapic_id, 0x16);
- }
-
- /* PCIe slot */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, ioapic_id, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x1, ioapic_id, 0x11);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 1);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 652d8cb..d25d0bc 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -207,21 +207,6 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042210;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0132;
- RCBA16(0x3142) = 0x3241;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3210;
- RCBA16(0x3148) = 0x3210;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Now, this is a bit ugly. As per PCI specification, function 0 of a
* device always has to be implemented. So disabling ethernet port 1
* would essentially disable all three ethernet ports of the mainboard.
diff --git a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
deleted file mode 100644
index e834ae1..0000000
--- a/src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x10 } // SATA
- })
- } Else {
- Return (Package() {
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA
- })
- }
-}
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 643cc7c..1d5f549 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -38,23 +38,22 @@ chip northbridge/intel/i945
end
end
- device pci 02.0 on # GMA Graphics controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # GMA Graphics controller
subsystemid 0x17aa 0x201a
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -74,14 +73,23 @@ chip northbridge/intel/i945
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
- device pci 1b.0 on # Audio Controller
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 # Audio Controller
subsystemid 0x17aa 0x2010
end
- device pci 1c.0 on # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 # Ethernet
subsystemid 0x17aa 0x2001
end
device pci 1c.1 on end # WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.1 on # USB UHCI
@@ -96,7 +104,9 @@ chip northbridge/intel/i945
device pci 1d.7 on # USB2 EHCI
subsystemid 0x17aa 0x200b
end
- device pci 1e.0 on # PCI Bridge
+ device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14 # PCI Bridge
chip southbridge/ti/pci1x2x
device pci 00.0 on
subsystemid 0x17aa 0x2012
@@ -106,7 +116,10 @@ chip northbridge/intel/i945
end
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
deleted file mode 100644
index 744ef30..0000000
--- a/src/mainboard/lenovo/t60/mptable.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */
-
- mptable_lintsrc(mc, isa_bus);
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 571a21c..8baeea6 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -118,25 +118,6 @@ static void rcba_config(void)
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00001230;
- RCBA32(0x3108) = 0x40004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00004321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000002;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl b/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
deleted file mode 100644
index e834ae1..0000000
--- a/src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
- Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
- Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
- Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
- Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
- Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
- Package() { 0x001dffff, 0, 0, 0x10 }, // USB
- Package() { 0x001dffff, 1, 0, 0x11 }, // USB
- Package() { 0x001dffff, 2, 0, 0x12 }, // USB
- Package() { 0x001dffff, 3, 0, 0x13 }, // USB
- Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
- Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
- Package() { 0x001fffff, 2, 0, 0x10 } // SATA
- })
- } Else {
- Return (Package() {
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
- Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 } // SATA
- })
- }
-}
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
index 91c9d73..5cf6ccf 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -37,22 +37,21 @@ chip northbridge/intel/i945
device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2017
end
- device pci 02.0 on # VGA controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 # VGA controller
subsystemid 0x17aa 0x201a
end
device pci 02.1 on # display controller
subsystemid 0x17aa 0x201a
end
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x0b"
- register "pirqf_routing" = "0x0b"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -74,11 +73,20 @@ chip northbridge/intel/i945
register "p_cnt_throttling_supported" = "1"
device pci 1b.0 on # Audio Controller
+ ioapic_irq 2 INTA 0x16
subsystemid 0x17aa 0x2010
end
- device pci 1c.0 on end # Ethernet
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # Ethernet
device pci 1c.1 on end # Atheros WLAN
- device pci 1d.0 on # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 # USB UHCI
subsystemid 0x17aa 0x200a
end
device pci 1d.1 on # USB UHCI
@@ -93,7 +101,10 @@ chip northbridge/intel/i945
device pci 1d.7 on # USB2 EHCI
subsystemid 0x17aa 0x200b
end
- device pci 1f.0 on # PCI-LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
deleted file mode 100644
index 8ade71b..0000000
--- a/src/mainboard/lenovo/x60/mptable.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */
-
- mptable_lintsrc(mc, isa_bus);
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index af9b1be..fbfbd7c 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -125,25 +125,6 @@ static void rcba_config(void)
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00001230;
- RCBA32(0x3108) = 0x40004321;
-
- /* PCIe Interrupts */
- RCBA32(0x310c) = 0x00004321;
- /* HD Audio Interrupt */
- RCBA32(0x3110) = 0x00000002;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x1007;
- RCBA16(0x3142) = 0x0076;
- RCBA16(0x3144) = 0x3210;
- RCBA16(0x3146) = 0x7654;
- RCBA16(0x3148) = 0x0010;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
diff --git a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl b/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
deleted file mode 100644
index 118319c..0000000
--- a/src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for the
- * i945
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
- If (PICM) {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, 0, 16 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, 0, 16 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, 0, 22 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, 0, 17 },
- Package() { 0x001cffff, 1, 0, 16 },
- Package() { 0x001cffff, 2, 0, 18 },
- Package() { 0x001cffff, 3, 0, 19 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, 0, 23 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 16 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, 0, 22 },
- Package() { 0x001effff, 1, 0, 20 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 19 },
- Package() { 0x001fffff, 1, 0, 20 },
- Package() { 0x001fffff, 3, 0, 16 }
- })
- } Else {
- Return (Package() {
- // PCIe Graphics 0:1.0
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // Onboard graphics (IGD) 0:2.0
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- // High Definition Audio 0:1b.0
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- // PCIe Root Ports 0:1c.x
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
- // USB and EHCI 0:1d.x
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
- // AC97 0:1e.2, 0:1e.3
- Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
- Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
- // LPC device 0:1f.0
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
- })
- }
-}
diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb
index 3fe8b2a..8e4a665 100644
--- a/src/mainboard/roda/rk886ex/devicetree.cb
+++ b/src/mainboard/roda/rk886ex/devicetree.cb
@@ -32,19 +32,18 @@ chip northbridge/intel/i945
device pci 00.0 on end # host bridge
# auto detection:
#device pci 01.0 off end # i945 PCIe root port
- device pci 02.0 on end # vga controller
+ device pci 02.0 on
+ ioapic_irq 2 INTA 0x10 end # vga controller
device pci 02.1 on end # display controller
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "0"
+ register "base" = "0xfec00000"
+ device ioapic 2 on end
+ end
chip southbridge/intel/i82801gx
- register "pirqa_routing" = "0x0b"
- register "pirqb_routing" = "0x0b"
- register "pirqc_routing" = "0x0b"
- register "pirqd_routing" = "0x0b"
- register "pirqe_routing" = "0x80"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x0b"
- register "pirqh_routing" = "0x0b"
-
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
@@ -63,19 +62,30 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
+ device pci 1b.0 on
+ ioapic_irq 2 INTA 0x16 end # High Definition Audio
+ device pci 1c.0 on
+ ioapic_irq 2 INTA 0x11
+ ioapic_irq 2 INTB 0x10
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x13 end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
+ device pci 1d.0 on
+ ioapic_irq 2 INTA 0x17
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTC 0x12
+ ioapic_irq 2 INTD 0x10 end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
+ ioapic_irq 2 INTA 0x16
+ ioapic_irq 2 INTB 0x14
chip southbridge/ti/pci7420
register "smartcard_enabled" = "0x0"
device pci 3.0 on end
@@ -86,7 +96,10 @@ chip northbridge/intel/i945
end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
+ device pci 1f.0 on
+ ioapic_irq 2 INTA 0x12
+ ioapic_irq 2 INTB 0x13
+ ioapic_irq 2 INTD 0x10 # LPC bridge
chip superio/smsc/lpc47n227
device pnp 2e.1 on # Parallel port
io 0x60 = 0x378
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
deleted file mode 100644
index 9b59bb4..0000000
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int isa_bus;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &isa_bus);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
-
- /* Legacy Interrupts */
- mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
-
- /* Builtin devices on Bus 0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
-
- /* Firewire 4:0.0 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
-
- // riser slot top 5:8.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
- // riser slot middle 5:9.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
- // riser slot bottom 5:a.0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
-
- /* Onboard Ethernet */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, isa_bus);
-
- /* Compute the checksums */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index e8ada36..c4bdcf4 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -154,21 +154,6 @@ static void rcba_config(void)
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
- /* Device 1f interrupt pin register */
- RCBA32(0x3100) = 0x00042220;
- /* Device 1d interrupt pin register */
- RCBA32(0x310c) = 0x00214321;
-
- /* dev irq route register */
- RCBA16(0x3140) = 0x0232;
- RCBA16(0x3142) = 0x3246;
- RCBA16(0x3144) = 0x0237;
- RCBA16(0x3146) = 0x3201;
- RCBA16(0x3148) = 0x3216;
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
-
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index df81689..a1204bc 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -234,6 +234,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/i945_pci_irqs.asl"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b12ad3a..08977f2 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -870,6 +870,27 @@ static void ich7_setup_pci_express(void)
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
}
+static void ich7_setup_interrupts(void)
+{
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042220;
+ RCBA32(0x3108) = 0x10004321;
+ /* Device 1d interrupt pin register */
+ RCBA32(0x310c) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(0x3110) = 0x00000001;
+
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0232;
+ RCBA16(0x3142) = 0x3246;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3201;
+ RCBA16(0x3148) = 0x3216;
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+}
+
void i945_early_initialization(void)
{
/* Print some chipset specific information */
@@ -922,6 +943,8 @@ static void i945_prepare_resume(int s3resume)
void i945_late_initialization(int s3resume)
{
+ ich7_setup_interrupts();
+
i945_setup_egress_port();
ich7_setup_root_complex_topology();
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index fe59ebe..a398453 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -355,6 +355,7 @@ void i945_late_initialization(int s3resume);
/* provided by mainboard code */
void setup_ich7_gpios(void);
+void southbridge_setup_interrupts(void);
/* debugging functions */
void print_pci_devices(void);
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 665a80a..2df94dd 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -190,3 +190,5 @@ Scope(\)
// SMBus
#include "smbus.asl"
+
+#include "irq.asl"
diff --git a/src/southbridge/intel/i82801gx/acpi/irq.asl b/src/southbridge/intel/i82801gx/acpi/irq.asl
new file mode 100644
index 0000000..1257371
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/acpi/irq.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // Network
+ Package() { 0x0007ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },
+ Package() { 0x001cffff, 1, 0, 16 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ // AC97 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 22 },
+ Package() { 0x001effff, 1, 0, 20 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 18 },
+ Package() { 0x001fffff, 1, 0, 19 },
+ Package() { 0x001fffff, 3, 0, 16 }
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Network 0:7.0
+ Package() { 0x0007ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // AC97 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+ })
+ }
+}
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 2bb81d6..589c082 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -21,18 +21,6 @@
#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
struct southbridge_intel_i82801gx_config {
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
/**
* GPI Routing configuration
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 6b9d11e..4e4c6ba 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -93,42 +93,37 @@ static void i82801gx_enable_serial_irqs(struct device *dev)
static void i82801gx_pirq_init(device_t dev)
{
device_t irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ /* Interrupt 11 is not used by legacy devices and so can always be used for
+ PCI interrupts. Full legacy IRQ routing is complicated and hard to
+ get right. Fortunately all modern OS use MSI and so it's not that big of
+ an issue anyway. Still we have to provide a reasonable default. Using
+ interrupt 11 for it everywhere is a working default. ACPI-aware OS can
+ move it to any interrupt and others will just leave them at default.
+ */
+ const u8 pirq_routing = 11;
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ pci_write_config8(dev, PIRQA_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQB_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQC_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQD_ROUT, pirq_routing);
- /* Eric Biederman once said we should let the OS do this.
- * I am not so sure anymore he was right.
- */
+ pci_write_config8(dev, PIRQE_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQF_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
+ pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
- }
-
- if (!int_line)
+ if (int_pin == 0)
continue;
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
}
}
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