[coreboot-gerrit] Patch merged into coreboot/master: cf52f97 intel/minnowmax: Update devicetree

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit cf52f9761fef3a8e46ff28d6593e0d573ff1d4ac
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Fri Dec 5 14:55:07 2014 -0700

    intel/minnowmax: Update devicetree
    
    - Align register values.
    
    - Enable both EHCI and XHCI so the choice of port used can be made
    at runtime.  When both are enabled in devicetree, XHCI currently gets
    disabled by the FSP chipset code.  This can be overridden in mainboard
    code or by a Kconfig entry, but there's a question about whether or not
    that's desired.
    
    - Enable function 1c.0 so the rest of the functions will be
    seen, even though the function is not actually used.  This is a
    short-term fix, as the correct solution is to determine whether or not
    any of the other functions are enabled, and not to hide function 0 if
    they are.  I am working on that, but I want to get this in for now.
    
    Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
    Reviewed-on: http://review.coreboot.org/7663
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>


See http://review.coreboot.org/7663 for details.

-gerrit