[coreboot-gerrit] New patch to review for coreboot: 06bae68 southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7692

-gerrit

commit 06bae6883bc4993c62c1e656cd8705c104af2d82
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Mon Dec 8 03:00:26 2014 +1100

    southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
    
    Correct mask to select bits 4-6 inclusively as per comment and use
    bitwise operations while working with bits. Be sure to write back out
    the data on the retrain.
    
    Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/southbridge/amd/sr5650/sr5650.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 7fdecf1..2a2d558 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -238,13 +238,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			if (reg & VC_NEGOTIATION_PENDING) {	/* bit1=1 means the link needs to be re-trained. */
 				/* set bit8=1, bit0-2=bit4-6 */
 				u32 tmp;
-				reg =
-				    nbpcie_p_read_index(dev,
-							PCIE_LC_LINK_WIDTH);
-				tmp = (reg >> 4) && 0x3;	/* get bit4-6 */
+				reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
+				tmp = (reg >> 4) & 0x7;	/* get bit4-6 */
 				reg &= 0xfff8;	/* clear bit0-2 */
 				reg += tmp;	/* merge */
 				reg |= 1 << 8;
+				nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
 				count++;	/* CIM said "keep in loop"?  */
 			} else {
 				res = 1;