[coreboot-gerrit] New patch to review for coreboot: 459d02b x86: provide symmetry between arm for cache_sync_instructions()

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7710

-gerrit

commit 459d02b3bd53ef86ac0ab66bf81b485b8dce3c7e
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Mar 25 15:31:00 2014 -0500

    x86: provide symmetry between arm for cache_sync_instructions()
    
    The arm architecture currently exports cache_sync_instructions()
    in <arch/cache.h>. In order for rmodule loading to work on arm
    architectures the cache_sync_instructions() needs to be called to
    sequence the instruction cache. To avoid sprinkling #ifdefs around
    just add an empty cache_sync_instructions() definition.
    
    BUG=chrome-os-partner:27094
    BRANCH=None
    TEST=Built and booted nyan and rambi.
    
    Original-Change-Id: I1a969757fffe0ca92754a0d953ba3630810556e3
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/191551
    Original-Reviewed-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit fda20947b928ee761d5ed15e414636af419970a6)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I3e8ca12e1d82ccedf1ff9851ae3c5c80cda2dd5f
---
 src/arch/x86/include/arch/cache.h | 41 +++++++++++++++++++++++++++++++++++++++
 src/lib/rmodule.c                 |  4 ++++
 2 files changed, 45 insertions(+)

diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h
new file mode 100644
index 0000000..687d3bf
--- /dev/null
+++ b/src/arch/x86/include/arch/cache.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef ARCH_CACHE_H
+#define ARCH_CACHE_H
+
+/*
+ * For the purposes of the currently executing CPU loading code that will be
+ * run there aren't any cache coherency operations required. This just provides
+ * symmetry between architectures.
+ */
+static inline void cache_sync_instructions(void) {}
+
+#endif /* ARCH_CACHE_H */
diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c
index a73e667..908297b 100644
--- a/src/lib/rmodule.c
+++ b/src/lib/rmodule.c
@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <arch/cache.h>
 #include <console/console.h>
 #include <rmodule.h>
 
@@ -196,6 +197,9 @@ int rmodule_load(void *base, struct rmodule *module)
 	if (rmodule_relocate(module))
 		return -1;
 	rmodule_clear_bss(module);
+
+	cache_sync_instructions();
+
 	return 0;
 }