[coreboot-gerrit] New patch to review for coreboot: 1be2080 nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7757

-gerrit

commit 1be2080e1f6d45d008e111778dafd7fa17702714
Author: Gabe Black <gabeblack at google.com>
Date:   Thu Apr 3 14:12:45 2014 -0700

    nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.
    
    This change takes about 8K of space away from the cbfs cache and repurposes
    it for the cbmem console buffer. This is a little more than twice the space
    we currently need for the bootblock and ROM stage to give us some room to grow
    and for extra debug output if needed.
    
    BUG=None
    TEST=Built and booted on nyan. Checked the cbmem output.
    BRANCH=None
    
    Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/193169
    Original-Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab
---
 src/mainboard/google/nyan/romstage.c       |  4 ++++
 src/mainboard/google/nyan_big/romstage.c   |  4 ++++
 src/mainboard/google/nyan_blaze/romstage.c |  4 ++++
 src/soc/nvidia/tegra124/Kconfig            | 13 +++++++++----
 4 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 10aeb54..cc1bfae 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index c239b4e..48d3842 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index c239b4e..48d3842 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -25,6 +25,7 @@
 #include <device/device.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -215,6 +216,9 @@ static void __attribute__((noinline)) romstage(void)
 				      "fallback/coreboot_ram");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 	stage_exit(entry);
 }
 
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index bdc4af9..7862dd5 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -30,8 +30,9 @@ config BOOTBLOCK_CPU_INIT
 #  so the bootblock loading address must be placed after that. After the
 #  handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
 #
-# 0x4000_0000 TTB (16KB).
-# 0x4000_4000 CBFS mapping cache (96KB).
+# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
+# 0x4000_4020 CBMEM console area (8K-32B)
+# 0x4000_6000 CBFS mapping cache (88K)
 # 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
 # 0x4002_0000 Bootblock (max 48KB).
 # 0x4002_C000 ROM stage (max 80KB).
@@ -85,11 +86,15 @@ config TTB_BUFFER
 
 config CBFS_CACHE_ADDRESS
 	hex "memory address to put CBFS cache data"
-	default 0x40004000
+	default 0x40006000
 
 config CBFS_CACHE_SIZE
 	hex "size of CBFS cache data"
-	default 0x00018000
+	default 0x00016000
+
+config CBMEM_CONSOLE_PRERAM_BASE
+	hex "memory address of the CBMEM console buffer"
+	default 0x40004020
 
 config TEGRA124_MODEL_TD570D
 	bool "TD570D"