[coreboot-gerrit] New patch to review for coreboot: 7657520 intel/minnowmax: Determine board type from GPIOs

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7797

-gerrit

commit 765752007e01054ced1bbf044e1e028746a67661
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Sun Dec 14 14:12:11 2014 -0700

    intel/minnowmax: Determine board type from GPIOs
    
    SSUS GPIO 5 reflects the Minnowboard Max SKU:
    --- GPIO 5 low is a 1GB board
    --- GPIO 5 high is a 2GB (or 4GB in the future) board.
    
    This allows us to determine the board type at runtime and configure
    the FSP appropriately.
    
    Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
 src/mainboard/intel/minnowmax/Kconfig    | 14 +-------------
 src/mainboard/intel/minnowmax/gpio.c     |  2 +-
 src/mainboard/intel/minnowmax/romstage.c | 19 +++++++++++++------
 3 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index 1a940b2..dfe4174 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -44,19 +44,7 @@ config LOCK_MANAGEMENT_ENGINE
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "Minnow Max 2GB" if MINNOWMAX_2GB_SKU
-	default "Minnow Max 1GB"
-
-choice
-	prompt "Memory SKU to build"
-	default MINNOWMAX_2GB_SKU
-
-config MINNOWMAX_1GB_SKU
-	bool "1GB"
-
-config MINNOWMAX_2GB_SKU
-	bool "2GB"
-endchoice
+	default "Minnow Max"
 
 config MAX_CPUS
 	int
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
index 9b735cf..defaf17 100644
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ b/src/mainboard/intel/minnowmax/gpio.c
@@ -179,7 +179,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
 	GPIO_FUNC(0, PULL_UP, 20K),		/* GPIO_S5[02] - SOC_GPIO_S5_2 */
 	GPIO_FUNC6,				/* GPIO_S5[03] - mPCIE_WAKEB */
 	GPIO_NC,				/* GPIO_S5[04] - No Connect */
-	GPIO_INPUT,				/* GPIO_S5[05] - BOM_OP1 */
+	GPIO_INPUT,				/* GPIO_S5[05] - BOM_OP1 - Memory: 0=1GB 1=2GB or 4GB*/
 	GPIO_INPUT,				/* GPIO_S5[06] - BOM_OP2 */
 	GPIO_INPUT,				/* GPIO_S5[07] - BOM_OP3 */
 	GPIO_OUT_HIGH,				/* GPIO_S5[08] - SOC_USB_HOST_EN0 */
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
index a144722..d8fd04a 100644
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ b/src/mainboard/intel/minnowmax/romstage.c
@@ -23,6 +23,7 @@
 #include <drivers/intel/fsp/fsp_util.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
+#include <baytrail/gpio.h>
 #include "chip.h"
 
 /**
@@ -57,17 +58,23 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 {
 	UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
 	u8 use_xhci = UpdData->PcdEnableXhci;
+	u8 gpio5 = 0;
 
 	/*
-	 * Minnow Max Board	: 1GB SKU uses 2Gb density memory
-	 *			  2GB SKU uses 4Gb densiry memory
+	 * Minnow Max Board
+	 * Read SSUS gpio 5 to determine memory type
+	 *                    0 : 1GB SKU uses 2Gb density memory
+	 *                    1 : 2GB SKU uses 4Gb density memory
 	 *
-	 * devicetree.cb assume 1GB SKU board
-	*/
-	if (CONFIG_MINNOWMAX_2GB_SKU)
+	 * devicetree.cb assumes 1GB SKU board
+	 */
+	configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
+	gpio5 = read_ssus_gpio(5);
+	if (gpio5)
 		UpdData->PcdMemoryParameters.DIMMDensity
 		+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
-
+	printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n",
+			gpio5 ? "2 / 4" : "1" );
 	/* Update XHCI UPD value if required */
 	get_option(&use_xhci, "use_xhci_over_ehci");
 	if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {