[coreboot-gerrit] Patch merged into coreboot/master: f296c94 tegra: spi: Read the command1 register to ensure the write to it completes.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f296c9452269ca22143004aa74f70e66288d4ddd
Author: Gabe Black <gabeblack at google.com>
Date:   Mon Apr 7 01:01:56 2014 -0700

    tegra: spi: Read the command1 register to ensure the write to it completes.
    
    To ensure that the command1 write which sets the "go" bit completes before
    other reads to the device. Otherwise, there's a race condition where those
    register values might still have their values from the last transfer. With
    different SPI clock frequencies, that could lead to spi_delay being told there
    were negative bytes still to send. Its expected delay would wrap to a negative
    value, that was passed to udelay, and the system would sit there for 4 seconds
    not doing anything.
    
    BUG=None
    TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was
    causing the 4+ second delay and verified that it no longer happened.
    BRANCH=None
    
    Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/193347
    Original-Reviewed-by: Gabe Black <gabeblack at chromium.org>
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a
    Reviewed-on: http://review.coreboot.org/7737
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/7737 for details.

-gerrit