[coreboot-gerrit] Patch merged into coreboot/master: 92dfa9c nyan*: Reduce the EC SPI bus frequency to 3 MHz.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 92dfa9c5814e7f0bb7830166a2fd7f2f04e336cb
Author: Gabe Black <gabeblack at google.com>
Date:   Mon Apr 7 01:19:27 2014 -0700

    nyan*: Reduce the EC SPI bus frequency to 3 MHz.
    
    The EC doesn't seem to be able to handle its bus running at 4 MHz or higher.
    To avoid it not being able to keep up, we reduce the frequency of that bus on
    all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we
    switch the clock source to CLKM.
    
    BUG=chrome-os-partner:22849
    TEST=Built and booted on nyan.
    BRANCH=None
    
    Original-Change-Id: I8f31b41098d64634427b4686f5333012f643fada
    Original-Signed-off-by: Gabe Black <gabeblack at google.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/193349
    Original-Commit-Queue: Gabe Black <gabeblack at chromium.org>
    Original-Tested-by: Gabe Black <gabeblack at chromium.org>
    Original-Reviewed-by: Gabe Black <gabeblack at chromium.org>
    (cherry picked from commit c215c50a5bb982b0e671c951e2fe8df06db85db2)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ia60513d118aed8881927e9d52f170e27655ea8e7
    Reviewed-on: http://review.coreboot.org/7739
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/7739 for details.

-gerrit