[coreboot-gerrit] New patch to review for coreboot: e5d28ab AGESA fam14: Increase MMCONF region

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7813

-gerrit

commit e5d28abdfa224dae4490b42f2be7a41ada3ea18b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sun Dec 14 16:36:09 2014 +0200

    AGESA fam14: Increase MMCONF region
    
    Increase to max 64 buses, as there are no benefits of limit 16.
    
    NOTE: It appears there is no matching (early) programming of the
    region to non-posted MMIO.
    
    Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/agesa/family14/Kconfig        |  2 +-
 src/northbridge/amd/agesa/family14/agesawrapper.c | 17 +----------------
 2 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig
index fef4b0a..3e73e5a 100644
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -37,6 +37,6 @@ config MMCONF_BASE_ADDRESS
 
 config MMCONF_BUS_NUMBER
 	int
-	default 16
+	default 64
 
 endif # NORTHBRIDGE_AMD_AGESA_FAMILY14
diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c
index 70d8918..fecec93 100644
--- a/src/northbridge/amd/agesa/family14/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family14/agesawrapper.c
@@ -34,8 +34,6 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-#define MMCONF_ENABLE 1
-
 /* Define AMD Ontario APPU SSID/SVID */
 #define AMD_APU_SVID		0x1022
 #define AMD_APU_SSID		0x1234
@@ -102,24 +100,11 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
 	PCI_ADDR PciAddress;
 	AMD_CONFIG_PARAMS StdHeader;
 
-	UINT8 BusRangeVal = 0;
-	UINT8 BusNum;
-	UINT8 Index;
-
 	/*
 	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
 	   Address MSR register.
 	 */
-
-	for (Index = 0; Index < 8; Index++) {
-		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
-		if (BusNum == 1) {
-			BusRangeVal = Index;
-			break;
-		}
-	}
-
-	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64) (BusRangeVal << 2) | MMCONF_ENABLE);
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
 	LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
 
 	/*