[coreboot-gerrit] Patch merged into coreboot/master: d712ec4 nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d712ec47d48f765dbc9008d94b58842d6c24b544
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date:   Mon Apr 14 12:47:37 2014 -0700

    nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register
    
    This register needs to be set properly during display init.
    
    BRANCH=none
    BUG=chrome-os-partner:27413
    TEST=build nyan and nyan_big. nyan display works fine.
         nyan_big display works as well. However, the mode setting
         needs to be based on either devicetree or EDID.
    
    Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
    
    Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031
    Original-Reviewed-on: https://chromium-review.googlesource.com/194739
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Commit-Queue: Hung-Te Lin <hungte at chromium.org>
    Original-Tested-by: Hung-Te Lin <hungte at chromium.org>
    (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c
    Reviewed-on: http://review.coreboot.org/7767
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/7767 for details.

-gerrit