[coreboot-gerrit] Patch set updated for coreboot: cfb156d x86: Initialize SPI controller explicitly during PCH init

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7756

-gerrit

commit cfb156de89f6167bf505e08a208dcae846501359
Author: David Hendricks <dhendrix at chromium.org>
Date:   Sun Apr 13 16:27:02 2014 -0700

    x86: Initialize SPI controller explicitly during PCH init
    
    This ensures that SPI is ready when eventlog code is used.
    
    x86 platforms which use eventlog invoke elog_clear() in GSMI and
    elog_add_event_raw() when deciding the boot path based on ME status.
    For the SMM case spi_init() is called during the finalize stage in
    SMM setup. For the boot path case we can call spi_init() at the
    beginning of BS_DEV_INIT and it will be ready to use when the boot
    path is determined from the ME status.
    
    BUG=none
    BRANCH=none
    TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi
    (Baytrail) with follow-up patch
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1
    Original-Reviewed-on: https://chromium-review.googlesource.com/194525
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Original-Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Original-Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad
---
 src/soc/intel/baytrail/spi.c       | 12 ++++++++++++
 src/southbridge/intel/common/spi.c |  9 +++++++++
 2 files changed, 21 insertions(+)

diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index 64aeb9b..8605dfc 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <bootstate.h>
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -316,6 +317,17 @@ void spi_init(void)
 	ich_set_bbar(0);
 }
 
+#ifndef __SMM__
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+        BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
+#endif
+
 int spi_claim_bus(struct spi_slave *slave)
 {
 	/* Handled by ICH automatically. */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 48c72b7..3f22bc7 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -26,6 +26,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <bootstate.h>
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
@@ -359,6 +360,14 @@ void spi_init(void)
 	bios_cntl &= ~(1 << 5);
 	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
 }
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+	BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
 
 int spi_claim_bus(struct spi_slave *slave)
 {