[coreboot-gerrit] New patch to review for coreboot: 4f6e189 baytrail: initialize backlight PWM frequency

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7845

-gerrit

commit 4f6e189c4f46c3dd9611f547fb4fdc1d2230b94c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Apr 24 11:35:28 2014 -0500

    baytrail: initialize backlight PWM frequency
    
    In order to protect ourselves from the kernel driver not honoring or
    placing the correct frequency in the backlight register always set one.
    This code path picks 200Hz as the default if nothing is specified in
    device tree. It's somewhat arbitrary but that frequency is valid for all
    the eDP panel specs we've seen being used on baytrail devices.
    
    BUG=chrome-os-partner:28267
    BRANCH=baytrail
    TEST=Built and booted in normal mode. Noted register write stuck.
    
    Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/196821
    Reviewed-by: Marc Jones <marc.jones at se-eng.com>
    (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 src/soc/intel/baytrail/chip.h |  2 ++
 src/soc/intel/baytrail/gfx.c  | 25 +++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 0860a96..f19055c 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -78,6 +78,7 @@ struct soc_intel_baytrail_config {
 	uint16_t gpu_pipea_power_off_delay;
 	uint16_t gpu_pipea_light_off_delay;
 	uint16_t gpu_pipea_power_cycle_delay;
+	int gpu_pipea_pwm_freq_hz;
 
 	int gpu_pipeb_port_select;	/* Port select: 1=DP_B 2=DP_C */
 	uint16_t gpu_pipeb_power_on_delay;
@@ -85,6 +86,7 @@ struct soc_intel_baytrail_config {
 	uint16_t gpu_pipeb_power_off_delay;
 	uint16_t gpu_pipeb_light_off_delay;
 	uint16_t gpu_pipeb_power_cycle_delay;
+	int gpu_pipeb_pwm_freq_hz;
 };
 
 extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 5650d0d..4cce877 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -290,6 +290,27 @@ static void gfx_post_vbios_init(device_t dev)
 	gfx_run_script(dev, gfx_post_vbios_script);
 }
 
+static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
+{
+	int divider;
+	struct resource *res;
+
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+
+	if (res == NULL)
+		return;
+
+	/* Default to 200 Hz if nothing is set. */
+	if (req_hz == 0)
+		req_hz = 200;
+
+	/* Base clock is 25MHz */
+	divider = 25 * 1000 * 1000 / (16 * req_hz);
+
+	/* Do not set duty cycle (lower 16 bits). Just set the divider. */
+	write32(res->base + bklt_reg, divider << 16);
+}
+
 static void gfx_panel_setup(device_t dev)
 {
 	struct soc_intel_baytrail_config *config = dev->chip_info;
@@ -333,11 +354,15 @@ static void gfx_panel_setup(device_t dev)
 	if (config->gpu_pipea_port_select) {
 		printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
 		reg_script_run_on_dev(dev, gfx_pipea_init);
+		set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL),
+		                  config->gpu_pipea_pwm_freq_hz);
 	}
 
 	if (config->gpu_pipeb_port_select) {
 		printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
 		reg_script_run_on_dev(dev, gfx_pipeb_init);
+		set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL),
+		                  config->gpu_pipeb_pwm_freq_hz);
 	}
 }