[coreboot-gerrit] Patch set updated for coreboot: 4381237 amd/olivehillplus/romstage.c: remove not useful variable 'halt'
Bruce Griffith (Bruce.Griffith@se-eng.com)
gerrit at coreboot.org
Wed Dec 17 23:18:30 CET 2014
Bruce Griffith (Bruce.Griffith at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7847
-gerrit
commit 4381237b831f9cebd7c4cf285612bda1452de3f2
Author: WANG Siyuan <wangsiyuanbuaa at gmail.com>
Date: Wed Dec 17 17:30:54 2014 +0800
amd/olivehillplus/romstage.c: remove not useful variable 'halt'
The variable 'halt' is not useful and results in a compile error
because of:
1b2f2a07 Introduce halt()
Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90
Signed-off-by: WANG Siyuan <SiYuan.Wang at amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa at gmail.com>
---
src/mainboard/amd/olivehillplus/romstage.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 367fa6a..f603d73 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -40,7 +40,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
- volatile int halt = 0;
/*
* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
@@ -64,9 +63,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
}
- if(boot_cpu()) {
- while(halt);
- }
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
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