[coreboot-gerrit] Patch set updated for coreboot: d7638dc intel/truxton: Add dummy cache-as-ram region
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Dec 19 14:10:53 CET 2014
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7863
-gerrit
commit d7638dc2b15e0084e728962ffbf00bd1b5e15666
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Dec 18 21:50:50 2014 +0200
intel/truxton: Add dummy cache-as-ram region
Board has no chance of working without a cache_as_ram.inc, but without
a specified CAR region we also break builds.
Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/ep80579/Kconfig | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig
index 530c48f..ec58428 100644
--- a/src/cpu/intel/ep80579/Kconfig
+++ b/src/cpu/intel/ep80579/Kconfig
@@ -5,3 +5,19 @@ config CPU_INTEL_EP80579
select ARCH_RAMSTAGE_X86_32
select SSE
select SUPPORT_CPU_UCODE_IN_CBFS
+ select BROKEN_CAR_MIGRATE
+
+if CPU_INTEL_EP80579
+
+# These are just dummy values to keep build happy.
+# This CPU does not have tested cache_as_ram.inc.
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffaf8000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif
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