[coreboot-gerrit] New patch to review for coreboot: 9a3aedc vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistent
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Mon Dec 22 08:48:07 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7886
-gerrit
commit 9a3aedc33844a35cc9c0a86baf161f275694e5a5
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Dec 22 18:46:18 2014 +1100
vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistent
Change-Id: I41ba4cffa545a31c1e0845ec44c8a433bda9f99d
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/vendorcode/amd/cimx/sb700/Makefile.inc | 4 +-
src/vendorcode/amd/cimx/sb700/SBPOR.c | 441 -----------------
src/vendorcode/amd/cimx/sb700/SBPort.c | 441 +++++++++++++++++
src/vendorcode/amd/cimx/sb800/Makefile.inc | 4 +-
src/vendorcode/amd/cimx/sb800/SBPOR.c | 366 --------------
src/vendorcode/amd/cimx/sb800/SBPort.c | 366 ++++++++++++++
src/vendorcode/amd/cimx/sb900/Makefile.inc | 4 +-
src/vendorcode/amd/cimx/sb900/SBPort.c | 737 +++++++++++++++++++++++++++++
src/vendorcode/amd/cimx/sb900/SbPor.c | 737 -----------------------------
9 files changed, 1550 insertions(+), 1550 deletions(-)
diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc
index ebd1cf2..aed81c4 100644
--- a/src/vendorcode/amd/cimx/sb700/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc
@@ -44,7 +44,7 @@ romstage-y += SATA.c
romstage-y += SBCMN.c
romstage-y += SBCMNLIB.c
romstage-y += SBMAIN.c
-romstage-y += SBPOR.c
+romstage-y += SBPort.c
romstage-y += SMM.c
romstage-y += USB.c
@@ -60,7 +60,7 @@ ramstage-y += SATA.c
ramstage-y += SBCMN.c
ramstage-y += SBCMNLIB.c
ramstage-y += SBMAIN.c
-ramstage-y += SBPOR.c
+ramstage-y += SBPort.c
ramstage-y += SMM.c
ramstage-y += USB.c
ramstage-y += LEGACY.c
diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c
deleted file mode 100644
index 6c5740b..0000000
--- a/src/vendorcode/amd/cimx/sb700/SBPOR.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *
- ***************************************************************************/
-
-
-#include "Platform.h"
-
-REG8MASK sbPorInitPciTable[] = {
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REGD0+2, 0x00, 0x01},
- {SB_SMBUS_REG40, 0x00, 0x44},
- {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
- {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
- {SB_SMBUS_REG64+1, 0x00, 0x78},
- {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
- {SB_SMBUS_REG64+3, 0x0F, 0x02},
- {SB_SMBUS_REG68+1, 0x00, 0x90},
- {SB_SMBUS_REG6C, 0x00, 0x20},
- {SB_SMBUS_REG78, 0x00, 0xFF},
- {SB_SMBUS_REG04, 0x00, 0x07},
- {SB_SMBUS_REG04+1, 0x00, 0x04},
- {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
- {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
- {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
- // can request SMI# to be sent out early before IO completion.
- // Some applications may have problems with this feature. The BIOS should set this bit
- // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
- {0xFF, 0xFF, 0xFF},
-
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG40, 0x00, 0x04},
- {SB_LPC_REG48, 0x00, 0x07},
- {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h.
- {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
- {SB_LPC_REG7C, 0x00, 0x05},
- {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
- {0xFF, 0xFF, 0xFF},
-
- // P2P Bridge(Bus 0, Dev 20, Func 4)
- {0x00, SBP2P_BUS_DEV_FUN, 0},
- {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
- {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
- {SB_P2P_REG1C, 0x00, 0x11},
- {SB_P2P_REG1D, 0x00, 0x11},
- {SB_P2P_REG04, 0x00, 0x21},
- {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window
- {0xFF, 0xFF, 0xFF},
-};
-
-
-REG8MASK sbA13PorInitPciTable[] = {
- // SMBUS Device(Bus 0, Dev 20, Func 0)
- {0x00, SMBUS_BUS_DEV_FUN, 0},
- {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
- {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
- {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode
- {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
- {0xFF, 0xFF, 0xFF},
-};
-
-
-REG8MASK sbA14PorInitPciTable[] = {
- // LPC Device(Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
- {0xFF, 0xFF, 0xFF},
-};
-
-REG8MASK sbPorPmioInitTbl[] = {
- // index andmask ormask
- {SB_PMIO_REG67, 0xFF, 0x02},
- {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge
- {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP
- {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker
- {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
- {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
- {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset
- {SB_PMIO_REGB2, 0xFF, BIT7},
- {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding
- {SB_PMIO_REGD7, 0xF6, 0x80},
- {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register
-
- {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown
- {SB_PMIO_REG52, 0xC0, 0x08},
-
- {SB_PMIO_REG8B, 0x00, 0x10},
- {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
-};
-
-REG8MASK sbA13PorPmioInitTbl[]={
- // index andmask ormask
- {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
- {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
- // Always clear [7] to begin with SP5100 C1e disabled
-
-// {SB_PMIO_REG65, 0xFF, BIT7},
-// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown
-// {SB_PMIO_REG52, 0xC0, 0x02},
-
-};
-
-
-void sbPowerOnInit (AMDSBCFG *pConfig){
- UINT8 dbVar0, dbVar1, dbValue;
- UINT16 dwTempVar;
- BUILDPARAM *pBuildOptPtr;
-
- TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
-
- setRevisionID();
- ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
- if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
-
- // Set A-Link bridge access address. This address is set at device 14h, function 0,
- // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry.
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
-
- writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access
- writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink(0x34, readAlink(0x34) | BIT9);
-
- if (!(pConfig->ResetCpuOnSyncFlood)){
- //Enable reset on sync flood
- writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
- (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
- }
-
- pBuildOptPtr = &(pConfig->BuildParameters);
-
- WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
-
- dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
- if( dwTempVar != 0 ){
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
- // Disable ASF Slave controller on SB700 rev A15.
- if (getRevisionID() == SB700_A15) {
- RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
- }
- }
-
- WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
- RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
-
- WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
- WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
- WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
- WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
- WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
- WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
- WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
- RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
- WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
-
- //Program power on pci init table
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
- //Program power on pmio init table
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
-
- dbValue = 0x00;
- ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
- dbValue &= 0xF3;
- WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
-
- if (getRevisionID() >= SB700_A13){
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
- programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
- }
-
- if ((getRevisionID() >= SB700_A14) )
- programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
-
- if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
- ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
- if (!(dbVar1 & BIT6)){
- RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
- pConfig->RebootRequired=1;
- }
- }
-
- if (getRevisionID() > SB700_A11) {
- if (pConfig->PciClk5 == 1)
- RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12
- }
-
- dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
- if (dbVar0 > 4) {
- dbVar0 = 0;
- }
- //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
-
- if (pConfig->Spi33Mhz)
- //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
- RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
-
- //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
- //from the existing value.
- ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
- if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
- pConfig->RebootRequired = 1;
- if (pConfig->SpreadSpectrum)
- RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
- else
- RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
-
- if ( !(pConfig->S3Resume) ){
- //To detect whether internal clock chip is used, do the following procedure
- //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
- //if it is 0, we are using clock chip on board.
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
-
- //Do the following programming only for SB700-A11.
- //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
- //2. Set PMIO_B2 [7]=0
- //3. Write the saved values from step 1, back to B0 and B1.
- //4. Set PMIO_B2 [6]=1.
- ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
- if (getRevisionID() == SB700_A11){
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
- WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
- RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
- }
-
- if (!(dwTempVar & BIT4)){
- RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
-
- //we are in external clock chip on the board
- if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
- //Configure usb clock to come from internal PLL
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
- }
- else{
- //Configure usb clock to come from external clock
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2
- }
- }
- else{
- //we are using internal clock chip on this board
- if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
- //Configure usb clock to come from internal PLL
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
- }
- else{
- //Configure usb clock to come from external clock
- RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
- RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2
- }
- }
-
- ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
- RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
- //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
- if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1;
- }
-
- if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- else
- RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
-
- if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
- RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
- RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
- RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
- }
-
- if (getRevisionID() >= SB700_A15) {
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
- //Enable unconditional shutdown fix in A15
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
- }
-
- // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
- if (isEcPresent()) {
- RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
- }
-
- //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
- // to program VID/FID LDTSTP# duration selection register
- AMDFamily15CpuLdtStopReq();
-
-#ifndef NO_EC_SUPPORT
- ecPowerOnInit(pBuildOptPtr, pConfig);
-#endif
-}
-
-
-void setRevisionID(void){
- UINT8 dbVar0, dbVar1;
-
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
- ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
- if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
- RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
- }
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
-}
-
-
-UINT8 getRevisionID(void){
- UINT8 dbVar0;
-
- ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
- return dbVar0;
-}
-
-
-void AMDFamily15CpuLdtStopReq(void) {
- CPUID_DATA CpuId;
- CPUID_DATA CpuId_Brand;
- UINT8 dbVar0, dbVar1, dbVar2;
-
- //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
- //to program VID/FID LDTSTP# duration selection register
- //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
- // 1. Any link in the system operating at a Gen 1 Frequency.
- // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
-
- CpuidRead (0x01, &CpuId);
- CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type
- if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
-
- //Program to Gen 3 default value - 001b
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b
-
- //Any link in the system operating at a Gen 1 Frequency.
- //Check Link 0 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
-
- if(dbVar2 == 0x01) {
- //Check Link 0 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 1 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 1 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 2 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 2 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- //Check Link 3 - Link connected regsister
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
- dbVar2 = dbVar2 & 0x01;
- if(dbVar2 == 0x01) {
- //Check Link 3 - Link Frequency Freq[4:0]
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
- ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
- dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
- dbVar1 = dbVar1 & 0x01; //Freq[4]
- dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0]
- //Value 6 or less indicate Gen1
- if(dbVar0 <= 0x6) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
- // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
- if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
- RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
- }
- }
-
-}
-
diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c
new file mode 100644
index 0000000..6c5740b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBPort.c
@@ -0,0 +1,441 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+REG8MASK sbPorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REGD0+2, 0x00, 0x01},
+ {SB_SMBUS_REG40, 0x00, 0x44},
+ {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
+ {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
+ {SB_SMBUS_REG64+1, 0x00, 0x78},
+ {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
+ {SB_SMBUS_REG64+3, 0x0F, 0x02},
+ {SB_SMBUS_REG68+1, 0x00, 0x90},
+ {SB_SMBUS_REG6C, 0x00, 0x20},
+ {SB_SMBUS_REG78, 0x00, 0xFF},
+ {SB_SMBUS_REG04, 0x00, 0x07},
+ {SB_SMBUS_REG04+1, 0x00, 0x04},
+ {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
+ {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
+ {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
+ // can request SMI# to be sent out early before IO completion.
+ // Some applications may have problems with this feature. The BIOS should set this bit
+ // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG40, 0x00, 0x04},
+ {SB_LPC_REG48, 0x00, 0x07},
+ {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h.
+ {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
+ {SB_LPC_REG7C, 0x00, 0x05},
+ {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
+ {0xFF, 0xFF, 0xFF},
+
+ // P2P Bridge(Bus 0, Dev 20, Func 4)
+ {0x00, SBP2P_BUS_DEV_FUN, 0},
+ {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
+ {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
+ {SB_P2P_REG1C, 0x00, 0x11},
+ {SB_P2P_REG1D, 0x00, 0x11},
+ {SB_P2P_REG04, 0x00, 0x21},
+ {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA13PorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
+ {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
+ {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode
+ {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA14PorInitPciTable[] = {
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
+ {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sbPorPmioInitTbl[] = {
+ // index andmask ormask
+ {SB_PMIO_REG67, 0xFF, 0x02},
+ {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge
+ {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP
+ {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker
+ {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
+ {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
+ {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset
+ {SB_PMIO_REGB2, 0xFF, BIT7},
+ {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding
+ {SB_PMIO_REGD7, 0xF6, 0x80},
+ {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register
+
+ {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown
+ {SB_PMIO_REG52, 0xC0, 0x08},
+
+ {SB_PMIO_REG8B, 0x00, 0x10},
+ {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
+};
+
+REG8MASK sbA13PorPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
+ {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
+ // Always clear [7] to begin with SP5100 C1e disabled
+
+// {SB_PMIO_REG65, 0xFF, BIT7},
+// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown
+// {SB_PMIO_REG52, 0xC0, 0x02},
+
+};
+
+
+void sbPowerOnInit (AMDSBCFG *pConfig){
+ UINT8 dbVar0, dbVar1, dbValue;
+ UINT16 dwTempVar;
+ BUILDPARAM *pBuildOptPtr;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+ setRevisionID();
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
+ if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
+
+ // Set A-Link bridge access address. This address is set at device 14h, function 0,
+ // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry.
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+
+ writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access
+ writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink(0x34, readAlink(0x34) | BIT9);
+
+ if (!(pConfig->ResetCpuOnSyncFlood)){
+ //Enable reset on sync flood
+ writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
+ (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
+ }
+
+ pBuildOptPtr = &(pConfig->BuildParameters);
+
+ WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
+
+ dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
+ if( dwTempVar != 0 ){
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
+ // Disable ASF Slave controller on SB700 rev A15.
+ if (getRevisionID() == SB700_A15) {
+ RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
+ }
+ }
+
+ WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
+
+ WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
+ WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
+ WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
+ WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
+ WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
+ WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
+ WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
+ RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
+ WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
+
+ //Program power on pci init table
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
+ //Program power on pmio init table
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
+
+ dbValue = 0x00;
+ ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+ dbValue &= 0xF3;
+ WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+
+ if (getRevisionID() >= SB700_A13){
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
+ }
+
+ if ((getRevisionID() >= SB700_A14) )
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
+
+ if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
+ ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
+ if (!(dbVar1 & BIT6)){
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
+ pConfig->RebootRequired=1;
+ }
+ }
+
+ if (getRevisionID() > SB700_A11) {
+ if (pConfig->PciClk5 == 1)
+ RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12
+ }
+
+ dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
+ if (dbVar0 > 4) {
+ dbVar0 = 0;
+ }
+ //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+
+ if (pConfig->Spi33Mhz)
+ //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
+ RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
+
+ //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
+ //from the existing value.
+ ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
+ if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
+ pConfig->RebootRequired = 1;
+ if (pConfig->SpreadSpectrum)
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
+ else
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
+
+ if ( !(pConfig->S3Resume) ){
+ //To detect whether internal clock chip is used, do the following procedure
+ //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
+ //if it is 0, we are using clock chip on board.
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+
+ //Do the following programming only for SB700-A11.
+ //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
+ //2. Set PMIO_B2 [7]=0
+ //3. Write the saved values from step 1, back to B0 and B1.
+ //4. Set PMIO_B2 [6]=1.
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ if (getRevisionID() == SB700_A11){
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
+ WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
+ }
+
+ if (!(dwTempVar & BIT4)){
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
+
+ //we are in external clock chip on the board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2
+ }
+ }
+ else{
+ //we are using internal clock chip on this board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2
+ }
+ }
+
+ ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
+ RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
+ //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
+ if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1;
+ }
+
+ if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ else
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+
+ if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
+ RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
+ RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+ //Enable unconditional shutdown fix in A15
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
+ }
+
+ // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
+ if (isEcPresent()) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
+ }
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ // to program VID/FID LDTSTP# duration selection register
+ AMDFamily15CpuLdtStopReq();
+
+#ifndef NO_EC_SUPPORT
+ ecPowerOnInit(pBuildOptPtr, pConfig);
+#endif
+}
+
+
+void setRevisionID(void){
+ UINT8 dbVar0, dbVar1;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
+ if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
+ }
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+}
+
+
+UINT8 getRevisionID(void){
+ UINT8 dbVar0;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ return dbVar0;
+}
+
+
+void AMDFamily15CpuLdtStopReq(void) {
+ CPUID_DATA CpuId;
+ CPUID_DATA CpuId_Brand;
+ UINT8 dbVar0, dbVar1, dbVar2;
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ //to program VID/FID LDTSTP# duration selection register
+ //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
+ // 1. Any link in the system operating at a Gen 1 Frequency.
+ // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+
+ CpuidRead (0x01, &CpuId);
+ CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type
+ if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
+
+ //Program to Gen 3 default value - 001b
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b
+
+ //Any link in the system operating at a Gen 1 Frequency.
+ //Check Link 0 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+
+ if(dbVar2 == 0x01) {
+ //Check Link 0 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 1 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 1 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 2 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 2 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 3 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 3 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+ if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc
index a035120..872f7ab 100644
--- a/src/vendorcode/amd/cimx/sb800/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc
@@ -33,7 +33,7 @@ romstage-y += PMIO2LIB.c
romstage-y += SATA.c
romstage-y += SBCMN.c
romstage-y += SBMAIN.c
-romstage-y += SBPOR.c
+romstage-y += SBPort.c
romstage-y += MEMLIB.c
romstage-y += PCILIB.c
romstage-y += IOLIB.c
@@ -57,7 +57,7 @@ ramstage-y += PMIO2LIB.c
ramstage-y += SATA.c
ramstage-y += SBCMN.c
ramstage-y += SBMAIN.c
-ramstage-y += SBPOR.c
+ramstage-y += SBPort.c
ramstage-y += MEMLIB.c
ramstage-y += PCILIB.c
ramstage-y += IOLIB.c
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c
deleted file mode 100644
index 048850d..0000000
--- a/src/vendorcode/amd/cimx/sb800/SBPOR.c
+++ /dev/null
@@ -1,366 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge Init during POWER-ON
- *
- * Prepare Southbridge environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "SBPLATFORM.h"
-#include "cbtypes.h"
-/**
- * sbPorInitPciTable - PCI device registers initial during the power on stage.
- */
-const static REG8MASK sbPorInitPciTable[] =
-{
- // SATA device
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG84 + 3, ~BIT2, 0},
- {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},
- {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
- {0xFF, 0xFF, 0xFF},
- // LPC Device (Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
- {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
- // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
- // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
- {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
- {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
- {0xFF, 0xFF, 0xFF},
- // P2P Bridge (Bus 0, Dev 20, Func 4)
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
- // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.
- {SB_PCIB_REG1C, 0x00, 0xF0},
- {SB_PCIB_REG1D, 0x00, 0x00},
- {SB_PCIB_REG04, 0x00, 0x21},
- {SB_PCIB_REG40, 0xDF, 0x20},
- {SB_PCIB_REG50, 0x02, 0x01},
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
- */
-const static AcpiRegWrite sbPmioPorInitTable[] =
-{
- {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
- {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
- {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
- {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
- // RPR GEC I/O Termination Setting
- // PM_Reg 0xF6 = Power-on default setting
- // PM_Reg 0xF7 = Power-on default setting
- // PM_Reg 0xF8 = 0x6C
- // PM_Reg 0xF9 = 0x21
- // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS
- {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
- {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},
- {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
-
- {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR
-
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPowerOnInit (
- IN AMDSBCFG* pConfig
- )
-{
-
- UINT8 dbPortStatus;
- UINT8 dbSysConfig;
- UINT32 abValue;
- UINT8 dbValue;
- UINT8 dbEfuse;
- UINT8 dbCg2WR;
- UINT8 dbCg1Pll;
- UINT8 cimNbSbGen2;
- UINT8 cimSataMode;
- UINT8 cimSpiFastReadEnable;
- UINT8 cimSpiFastReadSpeed;
- UINT8 cimSioHwmPortEnable;
- UINT8 SataPortNum;
-
- cimNbSbGen2 = pConfig->NbSbGen2;
- cimSataMode = pConfig->SATAMODE.SataModeReg;
-// Adding Fast Read Function support
- if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
- cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
- } else {
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- }
- cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
- cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
-#if SB_CIMx_PARAMETER == 0
- cimNbSbGen2 = cimNbSbGen2Default;
- cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
- cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
- cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
-#endif
-
-// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
- RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
-
-// Set A-Link bridge access address. This address is set at device 14h, function 0,
-// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
- writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction
- abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
- abValue = abValue | BIT0;
- writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
- writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink (0x34, readAlink (0x34) | BIT9);
-
- dbEfuse = FUSE_ID_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse == M1_D1_FUSE_ID ) {
- dbEfuse = MINOR_ID_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse == M1_MINOR_ID ) {
- // Limit ALink speed to 2.5G if Hudson-M1
- cimNbSbGen2 = 0;
- }
- }
-// Step 1:
-// AXINDP_Reg 0xA4[0] = 0x1
-// Step 2:
-// AXCFG_Reg 0x88[3:0] = 0x2
-// Step3:
-// AXINDP_Reg 0xA4[18] = 0x1
- if ( cimNbSbGen2 == TRUE ) {
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);
- rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);
- }
-
-// Set Build option into SB
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
- if (cimSioHwmPortEnable) {
- // Use Wide IO Port 1 to provide access to the superio HWM registers.
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
- }
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
-// Enabled SMBUS0/SMBUS1 (ASF) Base Address
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
-
- dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
-
- programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
-
-
- SataPortNum = 0;
- for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
- SbStall (2);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
- SbStall (2);
- }
-
-
- //The following bits must be set before enabling SPI prefetch.
- // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
- // if Ec is enable
- // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
- // else
- // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
- // the speed.
- getChipSysMode (&dbSysConfig);
- if (pConfig->BuildParameters.SpiSpeed < 0x02) {
- pConfig->BuildParameters.SpiSpeed = 0x01;
- if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;
- }
-
- if (pConfig->SbSpiSpeedSupport) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));
- }
- // SPI Fast Read Function
- if ( cimSpiFastReadEnable ) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);
- } else {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);
- }
-
- if ( cimSpiFastReadSpeed ) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
- }
- //Program power on pci init table
- programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
-// Change the CG PLL multiplier to x1.1
- if ( pConfig->UsbRxMode !=0 ) {
- dbCg2WR = 0x00;
- dbCg1Pll = 0x3A;
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);
- dbCg2WR &= BIT4;
- if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))
- {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);
- dbValue = 0x06;
- WriteIO (0xCF9, AccWidthUint8, &dbValue);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);
- }
- }
-
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );
-
- if (dbEfuse & BIT0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
- }
-
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
- if ( ((dbPortStatus & 0xF0) == 0x10) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
- }
-
- if ( pConfig->BuildParameters.LegacyFree ) {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- } else {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
- }
-
- dbValue = 0x09;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue & 0xF9;
- }
- if ( pConfig->BuildParameters.LegacyFree ) {
- // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
- dbValue = dbValue & 0x9F;
- }
- // Enabled IRQ input
- dbValue = dbValue | BIT4;
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
-#ifndef NO_EC_SUPPORT
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
- // EC is disabled by jumper setting or board config
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
- ecPowerOnInit ( pConfig);
- }
-#endif
-
- ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);
- if (dbValue & ChipSysIntClkGen) {
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);
- if (dbValue & BIT2) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);
- }
- }
-
- // Restore GPP clock to on as it may be off during last POST when some device was disabled;
- // the device can't be detected if enabled again as the values retain on S5 and warm reset.
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);
-
- // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
-}
diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c
new file mode 100644
index 0000000..048850d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SBPort.c
@@ -0,0 +1,366 @@
+
+/**
+ * @file
+ *
+ * Southbridge Init during POWER-ON
+ *
+ * Prepare Southbridge environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "SBPLATFORM.h"
+#include "cbtypes.h"
+/**
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.
+ */
+const static REG8MASK sbPorInitPciTable[] =
+{
+ // SATA device
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG84 + 3, ~BIT2, 0},
+ {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},
+ {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
+ {0xFF, 0xFF, 0xFF},
+ // LPC Device (Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+ {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
+ {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+ // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
+ // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+ {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+ {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
+ {0xFF, 0xFF, 0xFF},
+ // P2P Bridge (Bus 0, Dev 20, Func 4)
+ {0x00, PCIB_BUS_DEV_FUN, 0},
+ {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+ // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.
+ {SB_PCIB_REG1C, 0x00, 0xF0},
+ {SB_PCIB_REG1D, 0x00, 0x00},
+ {SB_PCIB_REG04, 0x00, 0x21},
+ {SB_PCIB_REG40, 0xDF, 0x20},
+ {SB_PCIB_REG50, 0x02, 0x01},
+ {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
+ */
+const static AcpiRegWrite sbPmioPorInitTable[] =
+{
+ {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+ {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
+ {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
+ // RPR GEC I/O Termination Setting
+ // PM_Reg 0xF6 = Power-on default setting
+ // PM_Reg 0xF7 = Power-on default setting
+ // PM_Reg 0xF8 = 0x6C
+ // PM_Reg 0xF9 = 0x21
+ // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
+
+ {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR
+
+ {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPowerOnInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+
+ UINT8 dbPortStatus;
+ UINT8 dbSysConfig;
+ UINT32 abValue;
+ UINT8 dbValue;
+ UINT8 dbEfuse;
+ UINT8 dbCg2WR;
+ UINT8 dbCg1Pll;
+ UINT8 cimNbSbGen2;
+ UINT8 cimSataMode;
+ UINT8 cimSpiFastReadEnable;
+ UINT8 cimSpiFastReadSpeed;
+ UINT8 cimSioHwmPortEnable;
+ UINT8 SataPortNum;
+
+ cimNbSbGen2 = pConfig->NbSbGen2;
+ cimSataMode = pConfig->SATAMODE.SataModeReg;
+// Adding Fast Read Function support
+ if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
+ cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
+ } else {
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ }
+ cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+ cimSioHwmPortEnable = pConfig->SioHwmPortEnable;
+#if SB_CIMx_PARAMETER == 0
+ cimNbSbGen2 = cimNbSbGen2Default;
+ cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
+ cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+ cimSioHwmPortEnable = cimSioHwmPortEnableDefault;
+#endif
+
+// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct
+ RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
+
+// Set A-Link bridge access address. This address is set at device 14h, function 0,
+// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+ writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction
+ abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
+ abValue = abValue | BIT0;
+ writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
+ writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink (0x34, readAlink (0x34) | BIT9);
+
+ dbEfuse = FUSE_ID_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse == M1_D1_FUSE_ID ) {
+ dbEfuse = MINOR_ID_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse == M1_MINOR_ID ) {
+ // Limit ALink speed to 2.5G if Hudson-M1
+ cimNbSbGen2 = 0;
+ }
+ }
+// Step 1:
+// AXINDP_Reg 0xA4[0] = 0x1
+// Step 2:
+// AXCFG_Reg 0x88[3:0] = 0x2
+// Step3:
+// AXINDP_Reg 0xA4[18] = 0x1
+ if ( cimNbSbGen2 == TRUE ) {
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);
+ rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);
+ }
+
+// Set Build option into SB
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+ if (cimSioHwmPortEnable) {
+ // Use Wide IO Port 1 to provide access to the superio HWM registers.
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes
+ }
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
+
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
+
+
+ SataPortNum = 0;
+ for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
+ SbStall (2);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
+ SbStall (2);
+ }
+
+
+ //The following bits must be set before enabling SPI prefetch.
+ // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).
+ // if Ec is enable
+ // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.
+ // else
+ // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at
+ // the speed.
+ getChipSysMode (&dbSysConfig);
+ if (pConfig->BuildParameters.SpiSpeed < 0x02) {
+ pConfig->BuildParameters.SpiSpeed = 0x01;
+ if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;
+ }
+
+ if (pConfig->SbSpiSpeedSupport) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));
+ }
+ // SPI Fast Read Function
+ if ( cimSpiFastReadEnable ) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);
+ } else {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);
+ }
+
+ if ( cimSpiFastReadSpeed ) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
+ }
+ //Program power on pci init table
+ programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+// Change the CG PLL multiplier to x1.1
+ if ( pConfig->UsbRxMode !=0 ) {
+ dbCg2WR = 0x00;
+ dbCg1Pll = 0x3A;
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);
+ dbCg2WR &= BIT4;
+ if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))
+ {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);
+ dbValue = 0x06;
+ WriteIO (0xCF9, AccWidthUint8, &dbValue);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);
+ }
+ }
+
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );
+
+ if (dbEfuse & BIT0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+ }
+
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
+ if ( ((dbPortStatus & 0xF0) == 0x10) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
+ }
+
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ } else {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+ }
+
+ dbValue = 0x09;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue & 0xF9;
+ }
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+ dbValue = dbValue & 0x9F;
+ }
+ // Enabled IRQ input
+ dbValue = dbValue | BIT4;
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+#ifndef NO_EC_SUPPORT
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
+ // EC is disabled by jumper setting or board config
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
+ ecPowerOnInit ( pConfig);
+ }
+#endif
+
+ ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);
+ if (dbValue & ChipSysIntClkGen) {
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);
+ if (dbValue & BIT2) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);
+ }
+ }
+
+ // Restore GPP clock to on as it may be off during last POST when some device was disabled;
+ // the device can't be detected if enabled again as the values retain on S5 and warm reset.
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);
+
+ // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);
+}
diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc
index ff26233..6cd932b 100644
--- a/src/vendorcode/amd/cimx/sb900/Makefile.inc
+++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc
@@ -33,7 +33,7 @@ romstage-y += Pmio2Lib.c
romstage-y += Sata.c
romstage-y += SbCmn.c
romstage-y += SbMain.c
-romstage-y += SbPor.c
+romstage-y += SBPort.c
romstage-y += MemLib.c
romstage-y += PciLib.c
romstage-y += IoLib.c
@@ -58,7 +58,7 @@ ramstage-y += Pmio2Lib.c
ramstage-y += Sata.c
ramstage-y += SbCmn.c
ramstage-y += SbMain.c
-ramstage-y += SbPor.c
+ramstage-y += SBPort.c
ramstage-y += MemLib.c
ramstage-y += PciLib.c
ramstage-y += IoLib.c
diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c
new file mode 100644
index 0000000..90e878e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/SBPort.c
@@ -0,0 +1,737 @@
+
+/**
+ * @file
+ *
+ * Southbridge Init during POWER-ON
+ *
+ * Prepare Southbridge environment during power on stage.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$ @e \$Date:$
+ *
+ */
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#include "SbPlatform.h"
+#include "cbtypes.h"
+#include "AmdSbLib.h"
+#include "Hudson-2.h"
+
+/**
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+REG8MASK sbPorInitPciTable[] =
+{
+ // SATA device
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG84 + 3, ~BIT2, 0},
+ {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
+ {0xFF, 0xFF, 0xFF},
+ // LPC Device (Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
+ {SB_LPC_REG47, 0xFF, BIT5},
+ {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
+ {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
+ {SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin
+ {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
+ // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
+ // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
+ {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
+ {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
+ {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
+ {0xFF, 0xFF, 0xFF},
+ // P2P Bridge (Bus 0, Dev 20, Func 4)
+ {0x00, PCIB_BUS_DEV_FUN, 0},
+ {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
+ // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
+ // ENH260809: Add PCI port 80 support in Hudson-2/3
+#ifdef SB_PCIB_PORT_80_SUPPORT
+ {SB_PCIB_REG1C, 0x00, 0xF0},
+ {SB_PCIB_REG1D, 0x00, 0x00},
+ {SB_PCIB_REG04, 0x00, 0x21},
+#endif
+ {SB_PCIB_REG40, 0xDF, 0x20},
+ {SB_PCIB_REG50, 0x02, 0x01},
+ {0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
+ *
+ *
+ *
+ *
+ */
+AcpiRegWrite sbPmioPorInitTable[] =
+{
+ {00, 00, 0xB0, 0xAC}, // Signature
+ {MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
+ //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
+ {MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00},
+// {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
+ {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
+ {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
+ {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
+ {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
+ //{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
+ {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
+ {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
+ {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
+ // RPR GEC I/O Termination Setting
+ // PM_Reg 0xF6 = Power-on default setting
+ // PM_Reg 0xF7 = Power-on default setting
+ // PM_Reg 0xF8 = 0x6C
+ // PM_Reg 0xF9 = 0x21
+ // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
+ // PRP GEC -end
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
+
+ {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},
+
+ //OBS200280
+ //{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1},
+
+
+ {0xFF, 0xFF, 0xFF, 0xFF},
+};
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+VOID
+sbPowerOnInit (
+ IN AMDSBCFG* pConfig
+ )
+{
+ UINT8 dbPortStatus;
+ //UINT8 dbSysConfig;
+ UINT32 abValue;
+ UINT32 abValue2;
+ UINT8 dbValue;
+ UINT8 dbEfuse;
+ UINT32 dbSpiMode;
+ UINT16 dwAsfPort;
+ UINT16 smbusBase;
+ UINT8 cimSataMode;
+// UINT8 cimSpiFastReadEnable;
+// UINT8 cimSpiFastReadSpeed;
+ UINT8 cimSataInternal100Spread;
+ UINT8 indexValue;
+ UINT32 ddValue;
+ UINT8 SataPortNum;
+ UINT8 XhciEfuse;
+ XhciEfuse = XHCI_EFUSE_LOCATION;
+
+ cimSataMode = pConfig->SATAMODE.SataModeReg;
+// if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
+// cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
+// } else {
+// cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+// }
+// cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
+ cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
+
+#if SB_CIMx_PARAMETER == 0
+ cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
+ cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
+ cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
+ cimSataInternal100Spread = SataInternal100SpreadDefault;
+#endif
+
+ TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
+ RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
+
+ RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
+ RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
+
+ if ( pConfig->Cg2Pll == 1 ) {
+ TurnOffCG2 ();
+ pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
+ }
+
+ //enable CF9
+ RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
+
+// Set A-Link bridge access address. This address is set at device 14h, function 0,
+// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+ writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
+ abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
+ abValue = abValue | BIT0;
+ writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
+ writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink (0x34, readAlink (0x34) | BIT9);
+ rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
+
+ // Enable external Stickybit register reset feature
+ //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
+ //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
+ //abValue |= BIT6 + BIT5;
+ //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
+
+ // Configure UMI target link speed
+ dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
+ getEfuseStatus (&dbEfuse);
+ if ( dbEfuse & BIT0 ) {
+ pConfig->NbSbGen2 = 0;
+ }
+
+ dbEfuse = FCH_Variant_EFUSE_LOCATION;
+ getEfuseStatus (&dbEfuse);
+ if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
+ pConfig->NbSbGen2 = 0;
+ }
+
+ if (pConfig->NbSbGen2) {
+ abValue = 2;
+ abValue2 = BIT0;
+ } else {
+ abValue = 1;
+ abValue2 = 0;
+ }
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
+ rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
+
+ if (pConfig->sdbEnable) {
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
+ RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
+ }
+
+// Set Build option into SB
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
+ smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
+ dbValue = 0x00;
+ WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
+
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
+ getEfuseStatus (&dbEfuse);
+
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
+
+ //RPR 3.4 Enabling ClkRun Function
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
+ //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
+
+ SataPortNum = 0;
+ for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
+ SbStall (2);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
+ SbStall (2);
+ }
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
+ if (pConfig->BuildParameters.SpiSpeed) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
+ }
+ if (pConfig->BuildParameters.SpiFastSpeed) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
+ }
+ //if (pConfig->BuildParameters.SpiBurstWrite) {
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
+ //}
+ dbSpiMode = pConfig->BuildParameters.SpiMode;
+ if (pConfig->BuildParameters.SpiMode) {
+ if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
+ // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
+ // SbStall (1000);
+ }
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
+ }
+
+// if ( cimSpiFastReadSpeed ) {
+// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
+// }
+ //Program power on pci init table
+ programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
+
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
+
+ if (pConfig->SATAMODE.SataModeReg == 0) {
+ pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
+ + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
+ + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
+ + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
+ + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
+ }
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
+
+ if (dbEfuse & BIT0) {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
+ }
+
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
+ if ( ((dbPortStatus & 0xF0) == 0x10) ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
+ }
+
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ } else {
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+ }
+
+ if ( cimSataInternal100Spread ) {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
+ }
+ // Toggle GEVENT4 to reset all GPP devices
+ sbGppTogglePcieReset (pConfig);
+
+ if ( cimSataInternal100Spread ) {
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
+ }
+
+ dbValue = 0x08;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue | 0x0A;
+ }
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+ dbValue = 0x09;
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+ if ( !pConfig->BuildParameters.EcKbd ) {
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
+ dbValue = dbValue & 0xF9;
+ }
+ if ( pConfig->BuildParameters.LegacyFree ) {
+ // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
+ dbValue = dbValue & 0x9F;
+ }
+ // Enabled IRQ input
+ dbValue = dbValue | BIT4;
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
+
+ dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
+ if ( dwAsfPort != 0 ) {
+ RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address)
+ }
+
+#ifndef NO_EC_SUPPORT
+ getChipSysMode (&dbPortStatus);
+ if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
+ // EC is disabled by jumper setting or board config
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
+ } else {
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
+ ecPowerOnInit ( pConfig);
+ imcSleep ( pConfig);
+ }
+#endif
+
+
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ if ( ddValue == 0x78121022 ) {
+//
+// First Xhci controller.
+//
+ ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ddValue = 0;
+ indexValue = XHCI_REGISTER_BAR03;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue = (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR02;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR01;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI_REGISTER_BAR00;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+ indexValue = XHCI_REGISTER_04H;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI_REGISTER_0CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI_REGISTER_3CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+//
+// Second Xhci controller.
+//
+ ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
+ ddValue = 0;
+ indexValue = XHCI1_REGISTER_BAR03;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue = (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR02;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR01;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+
+ indexValue = XHCI1_REGISTER_BAR00;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ ddValue <<= 8;
+ ddValue |= (UINT32) dbValue;
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
+
+ indexValue = XHCI1_REGISTER_04H;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI1_REGISTER_0CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
+
+ indexValue = XHCI1_REGISTER_3CH;
+ WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
+ ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
+ WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
+ }
+ // RPR 3.2 Enabling SPI ROM Prefetch
+ // Set LPC cfg 0xBA bit 8
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
+ if (IsSbA12Plus ()) {
+ // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
+ }
+#ifdef XHCI_SUPPORT
+#ifdef XHCI_INIT_IN_ROM_SUPPORT
+ if ( pConfig->XhciSwitch == 1 ) {
+ if ( pConfig->S3Resume == 0 ) {
+ XhciEarlyInit ();
+ } else {
+ XhciInitIndirectReg ();
+ }
+ } else {
+ // for power saving.
+
+ // add Efuse checking for Xhci enable/disable
+ getEfuseStatus (&XhciEfuse);
+ if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
+ }
+ }
+#endif
+#endif
+}
+
+#ifdef XHCI_SUPPORT
+VOID
+XhciInitIndirectReg (
+ )
+{
+ UINT32 ddDrivingStrength;
+ UINT32 port;
+ ddDrivingStrength = 0;
+ port = 0;
+#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
+ RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
+#endif
+//
+// RPR SuperSpeed PHY Configuration (adaptation mode setting)
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
+ RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
+//
+// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
+ RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
+
+//
+// RPR BLM Meaasge
+//
+ RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
+//
+// RPR 8.13 xHCI USB 2.0 PHY Settings
+// Step 1 is done by hardware default
+// Step 2
+#ifdef USB3_EHCI_DRIVING_STRENGTH
+ for (port = 0; port < 4; port ++) {
+ ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
+ if (ddDrivingStrength & BIT3) {
+ ddDrivingStrength &= 0x07;
+ if (port < 2) {
+ RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+ RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+ } else {
+ RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
+ RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
+ }
+ }
+ }
+#endif
+
+// Step 3
+ if (IsSbA11 ()) {
+ RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
+ RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
+ } else {
+ RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
+ RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
+ }
+}
+
+VOID
+XhciEarlyInit (
+ )
+{
+ UINT16 BcdAddress;
+ UINT16 BcdSize;
+ UINT16 AcdAddress;
+ UINT16 AcdSize;
+ UINT16 FwAddress;
+ UINT16 FwSize;
+ UINTN XhciFwStarting;
+ UINT32 SpiValidBase;
+ UINT32 RegData;
+ UINT16 i;
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
+ SbStall (20);
+//
+// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
+//
+ GetRomSigPtr (&XhciFwStarting);
+
+ if (XhciFwStarting == 0) {
+ return;
+ }
+
+ XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
+ if (IsLpcRom ()) {
+ //XHCI firmware re-load
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
+ }
+//
+// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
+// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
+// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
+//
+// RPR SuperSpeed PHY Configuration (adaptation timer setting)
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+ //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
+
+//
+// Step 1. to enable Xhci IO and Firmware load mode
+//
+
+#ifdef XHCI_SUPPORT_ONE_CONTROLLER
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
+#else
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
+#endif
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
+
+//
+// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
+//
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
+
+ BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
+ BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
+
+ AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
+ AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
+
+ SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
+
+ //
+ // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
+ //
+ for (i = 0; i < SPI_HEAD_LENGTH; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
+ }
+
+ for (i = 0; i < BcdSize; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
+ }
+
+ for (i = 0; i < AcdSize; i++) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
+ }
+
+//
+// Step 3. to enable the instruction RAM preload functionality.
+//
+ FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
+ FwAddress += 2;
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
+
+ FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
+
+ //
+ // Set the starting address offset for Instruction RAM preload.
+ //
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
+
+ for (;;) {
+ ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+ if (RegData & BIT30) break;
+ }
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
+
+//
+// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
+//
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
+ for (;;) {
+ ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
+ if (RegData & U3PLL_LOCK) break;
+ }
+
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
+
+// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
+ if (IsSbA11 ()) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
+ }
+
+ XhciInitIndirectReg ();
+
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
+ //if (!(pConfig->S4Resume)) {
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
+ //}
+//
+// Step 5.
+//
+ RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb900/SbPor.c b/src/vendorcode/amd/cimx/sb900/SbPor.c
deleted file mode 100644
index 90e878e..0000000
--- a/src/vendorcode/amd/cimx/sb900/SbPor.c
+++ /dev/null
@@ -1,737 +0,0 @@
-
-/**
- * @file
- *
- * Southbridge Init during POWER-ON
- *
- * Prepare Southbridge environment during power on stage.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: CIMx-SB
- * @e sub-project:
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#include "SbPlatform.h"
-#include "cbtypes.h"
-#include "AmdSbLib.h"
-#include "Hudson-2.h"
-
-/**
- * sbPorInitPciTable - PCI device registers initial during the power on stage.
- *
- *
- *
- *
- */
-REG8MASK sbPorInitPciTable[] =
-{
- // SATA device
- {0x00, SATA_BUS_DEV_FUN, 0},
- {SB_SATA_REG84 + 3, ~BIT2, 0},
- {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
- {0xFF, 0xFF, 0xFF},
- // LPC Device (Bus 0, Dev 20, Func 3)
- {0x00, LPC_BUS_DEV_FUN, 0},
- {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
- {SB_LPC_REG47, 0xFF, BIT5},
- {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
- {SB_LPC_REG7C, 0x00, BIT0 + BIT2},
- {SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin
- {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
- // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
- // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
- {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
- {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
- {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
- {0xFF, 0xFF, 0xFF},
- // P2P Bridge (Bus 0, Dev 20, Func 4)
- {0x00, PCIB_BUS_DEV_FUN, 0},
- {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
- // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
- // ENH260809: Add PCI port 80 support in Hudson-2/3
-#ifdef SB_PCIB_PORT_80_SUPPORT
- {SB_PCIB_REG1C, 0x00, 0xF0},
- {SB_PCIB_REG1D, 0x00, 0x00},
- {SB_PCIB_REG04, 0x00, 0x21},
-#endif
- {SB_PCIB_REG40, 0xDF, 0x20},
- {SB_PCIB_REG50, 0x02, 0x01},
- {0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
- *
- *
- *
- *
- */
-AcpiRegWrite sbPmioPorInitTable[] =
-{
- {00, 00, 0xB0, 0xAC}, // Signature
- {MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
- //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
- {MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00},
-// {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
- {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
- {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
- {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
- {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
- {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
- //{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
- {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
- {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
- {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
- {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
- {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
- {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
- // RPR GEC I/O Termination Setting
- // PM_Reg 0xF6 = Power-on default setting
- // PM_Reg 0xF7 = Power-on default setting
- // PM_Reg 0xF8 = 0x6C
- // PM_Reg 0xF9 = 0x21
- // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
- {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
- {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
- // PRP GEC -end
- {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST
- {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
-
- {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},
-
- //OBS200280
- //{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1},
-
-
- {0xFF, 0xFF, 0xFF, 0xFF},
-};
-
-/**
- * sbPowerOnInit - Config Southbridge during power on stage.
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-VOID
-sbPowerOnInit (
- IN AMDSBCFG* pConfig
- )
-{
- UINT8 dbPortStatus;
- //UINT8 dbSysConfig;
- UINT32 abValue;
- UINT32 abValue2;
- UINT8 dbValue;
- UINT8 dbEfuse;
- UINT32 dbSpiMode;
- UINT16 dwAsfPort;
- UINT16 smbusBase;
- UINT8 cimSataMode;
-// UINT8 cimSpiFastReadEnable;
-// UINT8 cimSpiFastReadSpeed;
- UINT8 cimSataInternal100Spread;
- UINT8 indexValue;
- UINT32 ddValue;
- UINT8 SataPortNum;
- UINT8 XhciEfuse;
- XhciEfuse = XHCI_EFUSE_LOCATION;
-
- cimSataMode = pConfig->SATAMODE.SataModeReg;
-// if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
-// cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
-// } else {
-// cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
-// }
-// cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
- cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
-
-#if SB_CIMx_PARAMETER == 0
- cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
- cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
- cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
- cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
- cimSataInternal100Spread = SataInternal100SpreadDefault;
-#endif
-
- TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
-
-// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
- RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
-
- RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
- RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
-
- if ( pConfig->Cg2Pll == 1 ) {
- TurnOffCG2 ();
- pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
- }
-
- //enable CF9
- RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
-
-// Set A-Link bridge access address. This address is set at device 14h, function 0,
-// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
- writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
- abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
- abValue = abValue | BIT0;
- writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
- writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
- writeAlink (0x34, readAlink (0x34) | BIT9);
- rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
-
- // Enable external Stickybit register reset feature
- //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
- //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
- //abValue |= BIT6 + BIT5;
- //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
-
- // Configure UMI target link speed
- dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
- getEfuseStatus (&dbEfuse);
- if ( dbEfuse & BIT0 ) {
- pConfig->NbSbGen2 = 0;
- }
-
- dbEfuse = FCH_Variant_EFUSE_LOCATION;
- getEfuseStatus (&dbEfuse);
- if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
- pConfig->NbSbGen2 = 0;
- }
-
- if (pConfig->NbSbGen2) {
- abValue = 2;
- abValue2 = BIT0;
- } else {
- abValue = 1;
- abValue2 = 0;
- }
- rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
- rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
-
- if (pConfig->sdbEnable) {
- rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
- RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
- }
-
-// Set Build option into SB
- WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
-// Enabled SMBUS0/SMBUS1 (ASF) Base Address
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
- smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
- dbValue = 0x00;
- WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
-
- dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
- getEfuseStatus (&dbEfuse);
-
- programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
-
- //RPR 3.4 Enabling ClkRun Function
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
- //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
-
- SataPortNum = 0;
- for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
- SbStall (2);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
- SbStall (2);
- }
-
- dbValue = 0x0A;
- WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
- dbValue &= 0xEF;
- WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
-
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
- if (pConfig->BuildParameters.SpiSpeed) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
- }
- if (pConfig->BuildParameters.SpiFastSpeed) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
- }
- //if (pConfig->BuildParameters.SpiBurstWrite) {
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
- //}
- dbSpiMode = pConfig->BuildParameters.SpiMode;
- if (pConfig->BuildParameters.SpiMode) {
- if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
- // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
- // SbStall (1000);
- }
- RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
- }
-
-// if ( cimSpiFastReadSpeed ) {
-// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
-// }
- //Program power on pci init table
- programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
-
- programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
-
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
-
- if (pConfig->SATAMODE.SataModeReg == 0) {
- pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
- + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
- + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
- + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
- + (pConfig->SATAMODE.SataMode.SataClkMode << 4);
- }
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
-
- if (dbEfuse & BIT0) {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
- }
-
- ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
- if ( ((dbPortStatus & 0xF0) == 0x10) ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
- }
-
- if ( pConfig->BuildParameters.LegacyFree ) {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
- } else {
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
- }
-
- if ( cimSataInternal100Spread ) {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
- } else {
- RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
- }
- // Toggle GEVENT4 to reset all GPP devices
- sbGppTogglePcieReset (pConfig);
-
- if ( cimSataInternal100Spread ) {
- RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
- }
-
- dbValue = 0x08;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue | 0x0A;
- }
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
- dbValue = 0x09;
- WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
- ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
- if ( !pConfig->BuildParameters.EcKbd ) {
- // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
- dbValue = dbValue & 0xF9;
- }
- if ( pConfig->BuildParameters.LegacyFree ) {
- // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
- dbValue = dbValue & 0x9F;
- }
- // Enabled IRQ input
- dbValue = dbValue | BIT4;
- WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
-
- dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
- if ( dwAsfPort != 0 ) {
- RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address)
- }
-
-#ifndef NO_EC_SUPPORT
- getChipSysMode (&dbPortStatus);
- if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
- // EC is disabled by jumper setting or board config
- RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
- } else {
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
- ecPowerOnInit ( pConfig);
- imcSleep ( pConfig);
- }
-#endif
-
-
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- if ( ddValue == 0x78121022 ) {
-//
-// First Xhci controller.
-//
- ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ddValue = 0;
- indexValue = XHCI_REGISTER_BAR03;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue = (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR02;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR01;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI_REGISTER_BAR00;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
- indexValue = XHCI_REGISTER_04H;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
- indexValue = XHCI_REGISTER_0CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
- indexValue = XHCI_REGISTER_3CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
-//
-// Second Xhci controller.
-//
- ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
- ddValue = 0;
- indexValue = XHCI1_REGISTER_BAR03;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue = (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR02;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR01;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
-
- indexValue = XHCI1_REGISTER_BAR00;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- ddValue <<= 8;
- ddValue |= (UINT32) dbValue;
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
-
- indexValue = XHCI1_REGISTER_04H;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
-
- indexValue = XHCI1_REGISTER_0CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
-
- indexValue = XHCI1_REGISTER_3CH;
- WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
- ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
- WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
- }
- // RPR 3.2 Enabling SPI ROM Prefetch
- // Set LPC cfg 0xBA bit 8
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
- if (IsSbA12Plus ()) {
- // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
- }
-#ifdef XHCI_SUPPORT
-#ifdef XHCI_INIT_IN_ROM_SUPPORT
- if ( pConfig->XhciSwitch == 1 ) {
- if ( pConfig->S3Resume == 0 ) {
- XhciEarlyInit ();
- } else {
- XhciInitIndirectReg ();
- }
- } else {
- // for power saving.
-
- // add Efuse checking for Xhci enable/disable
- getEfuseStatus (&XhciEfuse);
- if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
- }
- }
-#endif
-#endif
-}
-
-#ifdef XHCI_SUPPORT
-VOID
-XhciInitIndirectReg (
- )
-{
- UINT32 ddDrivingStrength;
- UINT32 port;
- ddDrivingStrength = 0;
- port = 0;
-#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
- RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
-#endif
-//
-// RPR SuperSpeed PHY Configuration (adaptation mode setting)
-//
- RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
- RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
-//
-// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
-//
- RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
- RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
-
-//
-// RPR BLM Meaasge
-//
- RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
-//
-// RPR 8.13 xHCI USB 2.0 PHY Settings
-// Step 1 is done by hardware default
-// Step 2
-#ifdef USB3_EHCI_DRIVING_STRENGTH
- for (port = 0; port < 4; port ++) {
- ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
- if (ddDrivingStrength & BIT3) {
- ddDrivingStrength &= 0x07;
- if (port < 2) {
- RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
- RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
- } else {
- RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
- RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
- }
- }
- }
-#endif
-
-// Step 3
- if (IsSbA11 ()) {
- RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
- RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
- } else {
- RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
- RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
- }
-}
-
-VOID
-XhciEarlyInit (
- )
-{
- UINT16 BcdAddress;
- UINT16 BcdSize;
- UINT16 AcdAddress;
- UINT16 AcdSize;
- UINT16 FwAddress;
- UINT16 FwSize;
- UINTN XhciFwStarting;
- UINT32 SpiValidBase;
- UINT32 RegData;
- UINT16 i;
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
- SbStall (20);
-//
-// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
-//
- GetRomSigPtr (&XhciFwStarting);
-
- if (XhciFwStarting == 0) {
- return;
- }
-
- XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
- if (IsLpcRom ()) {
- //XHCI firmware re-load
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
- RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
- }
-//
-// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
-// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
-// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
-//
-// RPR SuperSpeed PHY Configuration (adaptation timer setting)
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
- //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
-
-//
-// Step 1. to enable Xhci IO and Firmware load mode
-//
-
-#ifdef XHCI_SUPPORT_ONE_CONTROLLER
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
-#else
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
-#endif
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
-
-//
-// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
-//
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
-
- BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
- BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
-
- AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
- AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
-
- SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
-
- //
- // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
- //
- for (i = 0; i < SPI_HEAD_LENGTH; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
- }
-
- for (i = 0; i < BcdSize; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
- }
-
- for (i = 0; i < AcdSize; i++) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
- }
-
-//
-// Step 3. to enable the instruction RAM preload functionality.
-//
- FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
- FwAddress += 2;
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
-
- FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
-
- //
- // Set the starting address offset for Instruction RAM preload.
- //
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
-
- for (;;) {
- ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
- if (RegData & BIT30) break;
- }
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
-
-//
-// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
-//
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
- for (;;) {
- ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
- if (RegData & U3PLL_LOCK) break;
- }
-
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
-
-// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
- if (IsSbA11 ()) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
- }
-
- XhciInitIndirectReg ();
-
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
- RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
- //if (!(pConfig->S4Resume)) {
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
- //}
-//
-// Step 5.
-//
- RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
-}
-#endif
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