[coreboot-gerrit] Patch set updated for coreboot: 267082a soc/samsung/exynos5{25, 42}0: Merge common code
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Fri Dec 26 02:21:05 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7916
-gerrit
commit 267082a7e626233ec9c244975f898bfe227c2a48
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Dec 23 13:34:27 2014 +1100
soc/samsung/exynos5{25,42}0: Merge common code
[NOTFORMERGE]: First round at unifying Samsung Exynos SoC support
together.
Change-Id: Ib8f611375c4a44847737a969824492d84969525f
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/soc/samsung/Makefile.inc | 1 +
src/soc/samsung/exynos/Makefile.inc | 15 ++
src/soc/samsung/exynos/alternate_cbfs.h | 51 +++++++
src/soc/samsung/exynos/cbmem.c | 27 ++++
src/soc/samsung/exynos/dsim.h | 110 ++++++++++++++
src/soc/samsung/exynos/mct.c | 36 +++++
src/soc/samsung/exynos/monotonic_timer.c | 34 +++++
src/soc/samsung/exynos/power.c | 93 ++++++++++++
src/soc/samsung/exynos/uart.h | 43 ++++++
src/soc/samsung/exynos/usb.c | 198 ++++++++++++++++++++++++
src/soc/samsung/exynos/usb.h | 140 +++++++++++++++++
src/soc/samsung/exynos5250/Kconfig | 1 +
src/soc/samsung/exynos5250/Makefile.inc | 14 +-
src/soc/samsung/exynos5250/alternate_cbfs.h | 51 -------
src/soc/samsung/exynos5250/cbmem.c | 27 ----
src/soc/samsung/exynos5250/dsim.h | 110 --------------
src/soc/samsung/exynos5250/mct.c | 36 -----
src/soc/samsung/exynos5250/monotonic_timer.c | 34 -----
src/soc/samsung/exynos5250/power.c | 93 ------------
src/soc/samsung/exynos5250/uart.c | 3 +-
src/soc/samsung/exynos5250/uart.h | 42 ------
src/soc/samsung/exynos5250/usb.c | 198 ------------------------
src/soc/samsung/exynos5250/usb.h | 140 -----------------
src/soc/samsung/exynos5420/Kconfig | 1 +
src/soc/samsung/exynos5420/Makefile.inc | 16 +-
src/soc/samsung/exynos5420/alternate_cbfs.h | 51 -------
src/soc/samsung/exynos5420/cbmem.c | 27 ----
src/soc/samsung/exynos5420/dsim.h | 110 --------------
src/soc/samsung/exynos5420/mct.c | 36 -----
src/soc/samsung/exynos5420/monotonic_timer.c | 34 -----
src/soc/samsung/exynos5420/power.c | 93 ------------
src/soc/samsung/exynos5420/uart.c | 1 -
src/soc/samsung/exynos5420/uart.h | 42 ------
src/soc/samsung/exynos5420/usb.c | 217 ---------------------------
src/soc/samsung/exynos5420/usb.h | 147 ------------------
35 files changed, 758 insertions(+), 1514 deletions(-)
diff --git a/src/soc/samsung/Makefile.inc b/src/soc/samsung/Makefile.inc
index 496b5f7..e301ce1 100644
--- a/src/soc/samsung/Makefile.inc
+++ b/src/soc/samsung/Makefile.inc
@@ -1,2 +1,3 @@
subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5250) += exynos5250
subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5420) += exynos5420
+subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS) += exynos
diff --git a/src/soc/samsung/exynos/Makefile.inc b/src/soc/samsung/exynos/Makefile.inc
new file mode 100644
index 0000000..63b156b
--- /dev/null
+++ b/src/soc/samsung/exynos/Makefile.inc
@@ -0,0 +1,15 @@
+bootblock-y += mct.c power.c
+
+# Clock is required for UART
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c
+
+romstage-y += mct.c
+romstage-y += monotonic_timer.c
+romstage-y += cbmem.c
+romstage-y += power.c
+
+ramstage-y += mct.c
+ramstage-y += monotonic_timer.c
+ramstage-y += usb.c
+ramstage-y += cbmem.c
+ramstage-y += power.c
diff --git a/src/soc/samsung/exynos/alternate_cbfs.h b/src/soc/samsung/exynos/alternate_cbfs.h
new file mode 100644
index 0000000..771c0be
--- /dev/null
+++ b/src/soc/samsung/exynos/alternate_cbfs.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOSXXYY_ALTERNATE_CBFS_H
+#define CPU_SAMSUNG_EXYNOSXXYY_ALTERNATE_CBFS_H
+
+/* These are pointers to function pointers. Double indirection! */
+static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
+static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
+static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
+static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
+static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
+
+#define SECONDARY_BASE_BOOT_USB 0xfeed0002
+static u32 * const iram_secondary_base = (u32 *)0x02020018;
+
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
+#if defined(__BOOT_BLOCK__)
+ /* A small space in IRAM to hold the romstage-only image */
+ static void * const alternate_cbfs_buffer =
+ (void *)CONFIG_CBFS_CACHE_ADDRESS;
+ static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
+#else
+ /* Just put this anywhere in RAM that's far enough from anything else */
+ /* TODO: Find a better way to "reserve" this region? */
+ static void * const alternate_cbfs_buffer = (void *)0x77400000;
+ static size_t const alternate_cbfs_size = 0xc00000;
+#endif
+
+#endif /* CPU_SAMSUNG_EXYNOSXXYY_ALTERNATE_CBFS_H */
diff --git a/src/soc/samsung/exynos/cbmem.c b/src/soc/samsung/exynos/cbmem.c
new file mode 100644
index 0000000..d28882f
--- /dev/null
+++ b/src/soc/samsung/exynos/cbmem.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <cbmem.h>
+#include <cpu.h> // XXX: needed for get_fb_base_kb() static inline
+
+void *cbmem_top(void)
+{
+ return (void *)(get_fb_base_kb() * KiB);
+}
diff --git a/src/soc/samsung/exynos/dsim.h b/src/soc/samsung/exynos/dsim.h
new file mode 100644
index 0000000..fc0f9f9
--- /dev/null
+++ b/src/soc/samsung/exynos/dsim.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Register map for Exynos5 MIPI-DSIM */
+
+#ifndef CPU_SAMSUNG_EXYNOSXXYY_DSIM_H
+#define CPU_SAMSUNG_EXYNOSXXYY_DSIM_H
+
+/* DSIM register map */
+struct exynos5_dsim {
+ unsigned int status;
+ unsigned int swrst;
+ unsigned int clkctrl;
+ unsigned int timeout;
+ unsigned int config;
+ unsigned int escmode;
+ unsigned int mdresol;
+ unsigned int mvporch;
+ unsigned int mhporch;
+ unsigned int msync;
+ unsigned int sdresol;
+ unsigned int intsrc;
+ unsigned int intmsk;
+ unsigned int pkthdr;
+ unsigned int payload;
+ unsigned int rxfifo;
+ unsigned int res1;
+ unsigned int fifoctrl;
+ unsigned int res2;
+ unsigned int pllctrl;
+ unsigned int plltmr;
+ unsigned int phyacchr;
+ unsigned int phyacchr1;
+};
+check_member(exynos5_dsim, phyacchr1, 0x54);
+
+#define ENABLE 1
+#define DISABLE 0
+
+#define DSIM_SWRST (1 << 0)
+#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5)
+#define DATA_LANE_0_EN (1 << 0)
+#define DATA_LANE_1_EN (1 << 1)
+#define DATA_LANE_2_EN (1 << 2)
+#define DATA_LANE_3_EN (1 << 3)
+#define CLK_LANE_EN (1 << 4)
+#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \
+ DATA_LANE_1_EN | \
+ DATA_LANE_2_EN | \
+ DATA_LANE_3_EN
+#define MAIN_PIX_FORMAT_OFFSET 12
+#define RGB_565_16_BIT 0x4
+#define VIDEO_MODE (1 << 25)
+#define BURST_MODE (1 << 26)
+
+
+#define DSIM_PHYACCHR_AFC_EN (1 << 14)
+#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
+
+#define DSIM_PLLCTRL_PMS_OFFSET 1
+#define DSIM_FREQ_BAND_OFFSET 24
+
+#define LANE_ESC_CLK_EN_ALL (0x1f << 19)
+#define BYTE_CLK_EN (1 << 24)
+#define DSIM_ESC_CLK_EN (1 << 28)
+#define TXREQUEST_HS_CLK_ON (1 << 31)
+
+#define LP_MODE_ENABLE (1 << 7)
+#define STOP_STATE_CNT_OFFSET 21
+
+#define MAIN_VBP_OFFSET 0
+#define STABLE_VFP_OFFSET 16
+#define CMD_ALLOW_OFFSET 28
+
+#define MAIN_HBP_OFFSET 0
+#define MAIN_HFP_OFFSET 16
+
+#define MAIN_HSA_OFFSET 0
+#define MAIN_VSA_OFFSET 22
+
+#define MAIN_STANDBY (1 << 31)
+#define MAIN_VRESOL_OFFSET 16
+#define MAIN_HRESOL_OFFSET 0
+
+#define SFR_FIFO_EMPTY (1 << 29)
+
+#define DSIM_PLL_EN_SHIFT (1 << 23)
+#define PLL_STABLE (1 << 31)
+
+#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK (1 << 8)
+#define DSIM_TX_READY_HS_CLK (1 << 10)
+
+#endif /* CPU_SAMSUNG_EXYNOSXXYY_DSIM_H */
diff --git a/src/soc/samsung/exynos/mct.c b/src/soc/samsung/exynos/mct.c
new file mode 100644
index 0000000..bbb90e4
--- /dev/null
+++ b/src/soc/samsung/exynos/mct.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include "clk.h"
+
+uint64_t mct_raw_value(void)
+{
+ uint64_t upper = readl(&exynos_mct->g_cnt_u);
+ uint64_t lower = readl(&exynos_mct->g_cnt_l);
+
+ return (upper << 32) | lower;
+}
+
+void mct_start(void)
+{
+ writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+ &exynos_mct->g_tcon);
+}
diff --git a/src/soc/samsung/exynos/monotonic_timer.c b/src/soc/samsung/exynos/monotonic_timer.c
new file mode 100644
index 0000000..89ac416
--- /dev/null
+++ b/src/soc/samsung/exynos/monotonic_timer.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <timer.h>
+
+#include "clk.h"
+
+static const uint32_t clocks_per_usec = MCT_HZ/1000000;
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ /* We don't have to call mct_start() here
+ * because it was already called in the bootblock
+ */
+
+ mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec);
+}
diff --git a/src/soc/samsung/exynos/power.c b/src/soc/samsung/exynos/power.c
new file mode 100644
index 0000000..7d94712
--- /dev/null
+++ b/src/soc/samsung/exynos/power.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Power setup code for EXYNOS5 */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <halt.h>
+#include "dmc.h"
+#include "power.h"
+#include "setup.h"
+
+/* Set the PS-Hold drive value */
+static void ps_hold_setup(void)
+{
+ /* Set PS-Hold high */
+ setbits_le32(&exynos_power->ps_hold_ctrl,
+ POWER_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+void power_reset(void)
+{
+ /* Clear inform1 so there's no change we think we've got a wake reset */
+ exynos_power->inform1 = 0;
+
+ setbits_le32(&exynos_power->sw_reset, 1);
+}
+
+/* This function never returns */
+void power_shutdown(void)
+{
+ clrbits_le32(&exynos_power->ps_hold_ctrl,
+ POWER_PS_HOLD_CONTROL_DATA_HIGH);
+
+ halt();
+}
+
+void power_enable_dp_phy(void)
+{
+ setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
+}
+
+void power_enable_hw_thermal_trip(void)
+{
+ /* Enable HW thermal trip */
+ setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+}
+
+uint32_t power_read_reset_status(void)
+{
+ return exynos_power->inform1;
+}
+
+void power_exit_wakeup(void)
+{
+ typedef void (*resume_func)(void);
+
+ ((resume_func)exynos_power->inform0)();
+}
+
+int power_init(void)
+{
+ ps_hold_setup();
+ return 0;
+}
+
+void power_enable_xclkout(void)
+{
+ /* use xxti for xclk out */
+ clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+ PMU_DEBUG_XXTI);
+}
+
+void power_release_uart_retention(void)
+{
+ writel(1 << 28, &exynos_power->padret_uart_opt);
+}
diff --git a/src/soc/samsung/exynos/uart.h b/src/soc/samsung/exynos/uart.h
new file mode 100644
index 0000000..b7486ef
--- /dev/null
+++ b/src/soc/samsung/exynos/uart.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOSXXYY_UART_H
+#define CPU_SAMSUNG_EXYNOSXXYY_UART_H
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ unsigned char res3[0xffd0];
+};
+
+check_member(s5p_uart, ubrdiv, 0x28);
+
+#endif /* CPU_SAMSUNG_EXYNOSXXYY_UART_H */
diff --git a/src/soc/samsung/exynos/usb.c b/src/soc/samsung/exynos/usb.c
new file mode 100644
index 0000000..76da1dd
--- /dev/null
+++ b/src/soc/samsung/exynos/usb.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include "gpio.h"
+#include "power.h"
+#include "sysreg.h"
+#include "usb.h"
+
+static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
+{
+ setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */
+ setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
+ setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
+}
+
+void reset_usb_drd_dwc3()
+{
+ printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD\n");
+ reset_dwc3(exynos_usb_drd_dwc3);
+}
+
+static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
+{
+ if (!(dwc3->ctl & 0x1 << 11) ||
+ !(dwc3->usb3pipectl & 0x1 << 31) ||
+ !(dwc3->usb2phycfg & 0x1 << 31)) {
+ printk(BIOS_ERR, "DWC3 at %p not in reset (you need to call "
+ "reset_usb_drd_dwc3() first)!\n", dwc3);
+ }
+
+ /* Set relevant registers to default values (clearing all reset bits) */
+
+ writel(0x1 << 24 | /* activate PHY low power states */
+ 0x4 << 19 | /* low power delay value */
+ 0x1 << 18 | /* activate PHY low power delay */
+ 0x1 << 17 | /* enable SuperSpeed PHY suspend */
+ 0x1 << 1 | /* default Tx deemphasis value */
+ 0, &dwc3->usb3pipectl);
+
+ /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
+ writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */
+ 0x1 << 8 | /* enable PHY sleep in L1 */
+ 0x1 << 6 | /* enable PHY suspend */
+ 0, &dwc3->usb2phycfg);
+
+ writel(0x5dc << 19 | /* suspend clock scale for 24MHz */
+ 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */
+ 0x1 << 12 | /* port capability HOST */
+ 0, &dwc3->ctl);
+}
+
+void setup_usb_drd_dwc3()
+{
+ setup_dwc3(exynos_usb_drd_dwc3);
+ printk(BIOS_DEBUG, "DWC3 setup for USB DRD finished\n");
+}
+
+static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
+{
+ /* Set all PHY registers to default values */
+
+ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */
+ setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
+
+ /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
+ writel(1 << 6, &phy->utmi);
+
+ writel(0x88 << 23 | /* spread spectrum refclk selector */
+ 0x1 << 20 | /* enable spread spectrum */
+ 0x1 << 19 | /* enable prescaler refclk */
+ 0x68 << 11 | /* multiplier for 24MHz refclk */
+ 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */
+ 0x1 << 4 | /* power supply in normal operating mode */
+ 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/
+ 0x1 << 1 | /* force port reset */
+ 0x1 << 0 | /* normal operating mode */
+ 0, &phy->clkrst);
+
+ writel(0x9 << 26 | /* LOS level */
+ 0x3 << 22 | /* TX VREF tune */
+ 0x1 << 20 | /* TX rise tune */
+ 0x1 << 18 | /* TX res tune */
+ 0x3 << 13 | /* TX HS X Vtune */
+ 0x3 << 9 | /* TX FS/LS tune */
+ 0x3 << 6 | /* SQRX tune */
+ 0x4 << 3 | /* OTG tune */
+ 0x4 << 0 | /* comp disc tune */
+ 0, &phy->param0);
+
+ writel(0x7f << 19 | /* reserved */
+ 0x7f << 12 | /* Tx launch amplitude */
+ 0x20 << 6 | /* Tx deemphasis 6dB */
+ 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */
+ 0, &phy->param1);
+
+ /* disable all test features */
+ writel(0, &phy->test);
+
+ /* UTMI clock select? ("must be 0x1") */
+ writel(0x1 << 2, &phy->utmiclksel);
+
+ /* Samsung magic, undocumented (from U-Boot) */
+ writel(0x0, &phy->resume);
+
+ udelay(10);
+ clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
+}
+
+void setup_usb_drd_phy()
+{
+ printk(BIOS_DEBUG, "Powering up USB DRD PHY\n");
+ setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+ setup_drd_phy(exynos_usb_drd_phy);
+}
+
+void setup_usb_host_phy(int hsic_gpio)
+{
+ unsigned int hostphy_ctrl0;
+
+ setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+ setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
+
+ printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
+ hsic_gpio ? "with" : "without");
+
+ hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
+ hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
+ HOST_CTRL0_COMMONON_N |
+ /* HOST Phy setting */
+ HOST_CTRL0_PHYSWRST |
+ HOST_CTRL0_PHYSWRSTALL |
+ HOST_CTRL0_SIDDQ |
+ HOST_CTRL0_FORCESUSPEND |
+ HOST_CTRL0_FORCESLEEP);
+ hostphy_ctrl0 |= (/* Setting up the ref freq */
+ CLK_24MHZ << 16 |
+ /* HOST Phy setting */
+ HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST);
+ writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
+ udelay(10);
+ clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
+ HOST_CTRL0_LINKSWRST |
+ HOST_CTRL0_UTMISWRST);
+ udelay(20);
+
+ /* EHCI Ctrl setting */
+ setbits_le32(&exynos_usb_host_phy->ehcictrl,
+ EHCICTRL_ENAINCRXALIGN |
+ EHCICTRL_ENAINCR4 |
+ EHCICTRL_ENAINCR8 |
+ EHCICTRL_ENAINCR16);
+
+ /* HSIC USB Hub initialization. */
+ if (hsic_gpio) {
+ gpio_direction_output(hsic_gpio, 0);
+ udelay(100);
+ gpio_direction_output(hsic_gpio, 1);
+ udelay(5000);
+
+ clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_SIDDQ |
+ HOST_CTRL0_FORCESLEEP |
+ HOST_CTRL0_FORCESUSPEND);
+ setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
+ udelay(10);
+ clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
+ }
+
+ /* At this point we need to wait for 50ms before talking to
+ * the USB controller (PHY clock and power setup time)
+ * By the time we are actually in the payload, these 50ms
+ * will have passed.
+ */
+}
diff --git a/src/soc/samsung/exynos/usb.h b/src/soc/samsung/exynos/usb.h
new file mode 100644
index 0000000..20a2257
--- /dev/null
+++ b/src/soc/samsung/exynos/usb.h
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_SAMSUNG_EXYNOS5250_USB_H
+#define CPU_SAMSUNG_EXYNOS5250_USB_H
+
+#include "cpu.h"
+
+#define CLK_24MHZ 5
+
+#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
+#define HOST_CTRL0_COMMONON_N (1 << 9)
+#define HOST_CTRL0_SIDDQ (1 << 6)
+#define HOST_CTRL0_FORCESLEEP (1 << 5)
+#define HOST_CTRL0_FORCESUSPEND (1 << 4)
+#define HOST_CTRL0_WORDINTERFACE (1 << 3)
+#define HOST_CTRL0_UTMISWRST (1 << 2)
+#define HOST_CTRL0_LINKSWRST (1 << 1)
+#define HOST_CTRL0_PHYSWRST (1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN (1 << 29)
+#define EHCICTRL_ENAINCR4 (1 << 28)
+#define EHCICTRL_ENAINCR8 (1 << 27)
+#define EHCICTRL_ENAINCR16 (1 << 26)
+
+/* Register map for PHY control */
+struct exynos5_usb_host_phy {
+ uint32_t usbphyctrl0;
+ uint32_t usbphytune0;
+ uint8_t reserved1[8];
+ uint32_t hsicphyctrl1;
+ uint32_t hsicphytune1;
+ uint8_t reserved2[8];
+ uint32_t hsicphyctrl2;
+ uint32_t hsicphytune2;
+ uint8_t reserved3[8];
+ uint32_t ehcictrl;
+ uint32_t ohcictrl;
+ uint32_t usbotgsys;
+ uint8_t reserved4[4];
+ uint32_t usbotgtune;
+};
+check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
+
+static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
+ (void *)EXYNOS5_USB_HOST_PHY_BASE;
+
+struct exynos5_usb_drd_phy {
+ uint8_t reserved1[4];
+ uint32_t linksystem;
+ uint32_t utmi;
+ uint32_t pipe;
+ uint32_t clkrst;
+ uint32_t reg0;
+ uint32_t reg1;
+ uint32_t param0;
+ uint32_t param1;
+ uint32_t term;
+ uint32_t test;
+ uint32_t adp;
+ uint32_t utmiclksel;
+ uint32_t resume;
+ uint8_t reserved2[8];
+ uint32_t linkhcbelt;
+ uint32_t linkport;
+};
+check_member(exynos5_usb_drd_phy, linkport, 0x44);
+
+static struct exynos5_usb_drd_phy * const exynos_usb_drd_phy =
+ (void *)EXYNOS5_USB_DRD_PHY_BASE;
+
+struct exynos5_usb_drd_dwc3 {
+ uint32_t sbuscfg0;
+ uint32_t sbuscfg1;
+ uint32_t txthrcfg;
+ uint32_t rxthrcfg;
+ uint32_t ctl;
+ uint32_t evten;
+ uint32_t sts;
+ uint8_t reserved0[4];
+ uint32_t snpsid;
+ uint32_t gpio;
+ uint32_t uid;
+ uint32_t uctl;
+ uint64_t buserraddr;
+ uint64_t prtbimap;
+ uint8_t reserved1[32];
+ uint32_t dbgfifospace;
+ uint32_t dbgltssm;
+ uint32_t dbglnmcc;
+ uint32_t dbgbmu;
+ uint32_t dbglspmux;
+ uint32_t dbglsp;
+ uint32_t dbgepinfo0;
+ uint32_t dbgepinfo1;
+ uint64_t prtbimap_hs;
+ uint64_t prtbimap_fs;
+ uint8_t reserved2[112];
+ uint32_t usb2phycfg;
+ uint8_t reserved3[60];
+ uint32_t usb2i2cctl;
+ uint8_t reserved4[60];
+ uint32_t usb2phyacc;
+ uint8_t reserved5[60];
+ uint32_t usb3pipectl;
+ uint8_t reserved6[60];
+};
+check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
+
+static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd_dwc3 =
+ (void *)EXYNOS5_USB_DRD_DWC3_BASE;
+
+/* Leave hsic_gpio at 0 to not enable HSIC. */
+void setup_usb_host_phy(int hsic_gpio);
+
+void setup_usb_drd_phy(void);
+
+/* Call reset_ before setup_, ensure at least 100ms pass in between. */
+void reset_usb_drd_dwc3(void);
+void setup_usb_drd_dwc3(void);
+
+#endif
diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig
index 8d7c867..92d3e70 100644
--- a/src/soc/samsung/exynos5250/Kconfig
+++ b/src/soc/samsung/exynos5250/Kconfig
@@ -2,6 +2,7 @@ config CPU_SAMSUNG_EXYNOS5250
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
+ select CPU_SAMSUNG_EXYNOS
select CPU_HAS_BOOTBLOCK_INIT
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 735ce2e..ddc2213 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -1,10 +1,9 @@
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += bootblock.c
-bootblock-y += pinmux.c mct.c power.c
+bootblock-y += pinmux.c
# Clock is required for UART
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c
-bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c
ifeq ($(CONFIG_DRIVERS_UART),y)
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
endif
@@ -18,9 +17,6 @@ romstage-y += clock_init.c
romstage-y += pinmux.c # required by s3c24x0_i2c and uart.
romstage-y += dmc_common.c
romstage-y += dmc_init_ddr3.c
-romstage-y += power.c
-romstage-y += mct.c
-romstage-y += monotonic_timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += wakeup.c
romstage-y += gpio.c
@@ -28,25 +24,21 @@ romstage-y += timer.c
romstage-y += trustzone.c
romstage-y += i2c.c
#romstage-y += wdt.c
-romstage-y += cbmem.c
ramstage-y += spi.c alternate_cbfs.c
ramstage-y += clock.c
ramstage-y += clock_init.c
ramstage-y += pinmux.c
-ramstage-y += power.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += cpu.c
ramstage-y += tmu.c
-ramstage-y += mct.c
-ramstage-y += monotonic_timer.c
ramstage-y += timer.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += dp-reg.c
ramstage-y += fb.c
-ramstage-y += usb.c
-ramstage-y += cbmem.c
+
+CPPFLAGS_common += -Isrc/soc/samsung/exynos/
$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
cp $< $@
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.h b/src/soc/samsung/exynos5250/alternate_cbfs.h
deleted file mode 100644
index 72a30ac..0000000
--- a/src/soc/samsung/exynos5250/alternate_cbfs.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
-#define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
-
-/* These are pointers to function pointers. Double indirection! */
-static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
-static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
-static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
-static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
-static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
-
-#define SECONDARY_BASE_BOOT_USB 0xfeed0002
-static u32 * const iram_secondary_base = (u32 *)0x02020018;
-
-/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
-#define OM_STAT_SDMMC 0x4
-#define OM_STAT_EMMC 0x8
-#define OM_STAT_SPI 0x14
-#define OM_STAT_MASK 0x7f
-
-#if defined(__BOOT_BLOCK__)
- /* A small space in IRAM to hold the romstage-only image */
- static void * const alternate_cbfs_buffer =
- (void *)CONFIG_CBFS_CACHE_ADDRESS;
- static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
-#else
- /* Just put this anywhere in RAM that's far enough from anything else */
- /* TODO: Find a better way to "reserve" this region? */
- static void * const alternate_cbfs_buffer = (void *)0x77400000;
- static size_t const alternate_cbfs_size = 0xc00000;
-#endif
-
-#endif
diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c
deleted file mode 100644
index 4650320..0000000
--- a/src/soc/samsung/exynos5250/cbmem.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stddef.h>
-#include <cbmem.h>
-#include "cpu.h"
-
-void *cbmem_top(void)
-{
- return (void *)(get_fb_base_kb() * KiB);
-}
diff --git a/src/soc/samsung/exynos5250/dsim.h b/src/soc/samsung/exynos5250/dsim.h
deleted file mode 100644
index b975a10..0000000
--- a/src/soc/samsung/exynos5250/dsim.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Register map for Exynos5 MIPI-DSIM */
-
-#ifndef CPU_SAMSUNG_EXYNOS5250_DSIM_H
-#define CPU_SAMSUNG_EXYNOS5250_DSIM_H
-
-/* DSIM register map */
-struct exynos5_dsim {
- unsigned int status;
- unsigned int swrst;
- unsigned int clkctrl;
- unsigned int timeout;
- unsigned int config;
- unsigned int escmode;
- unsigned int mdresol;
- unsigned int mvporch;
- unsigned int mhporch;
- unsigned int msync;
- unsigned int sdresol;
- unsigned int intsrc;
- unsigned int intmsk;
- unsigned int pkthdr;
- unsigned int payload;
- unsigned int rxfifo;
- unsigned int res1;
- unsigned int fifoctrl;
- unsigned int res2;
- unsigned int pllctrl;
- unsigned int plltmr;
- unsigned int phyacchr;
- unsigned int phyacchr1;
-};
-check_member(exynos5_dsim, phyacchr1, 0x54);
-
-#define ENABLE 1
-#define DISABLE 0
-
-#define DSIM_SWRST (1 << 0)
-#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5)
-#define DATA_LANE_0_EN (1 << 0)
-#define DATA_LANE_1_EN (1 << 1)
-#define DATA_LANE_2_EN (1 << 2)
-#define DATA_LANE_3_EN (1 << 3)
-#define CLK_LANE_EN (1 << 4)
-#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \
- DATA_LANE_1_EN | \
- DATA_LANE_2_EN | \
- DATA_LANE_3_EN
-#define MAIN_PIX_FORMAT_OFFSET 12
-#define RGB_565_16_BIT 0x4
-#define VIDEO_MODE (1 << 25)
-#define BURST_MODE (1 << 26)
-
-
-#define DSIM_PHYACCHR_AFC_EN (1 << 14)
-#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
-
-#define DSIM_PLLCTRL_PMS_OFFSET 1
-#define DSIM_FREQ_BAND_OFFSET 24
-
-#define LANE_ESC_CLK_EN_ALL (0x1f << 19)
-#define BYTE_CLK_EN (1 << 24)
-#define DSIM_ESC_CLK_EN (1 << 28)
-#define TXREQUEST_HS_CLK_ON (1 << 31)
-
-#define LP_MODE_ENABLE (1 << 7)
-#define STOP_STATE_CNT_OFFSET 21
-
-#define MAIN_VBP_OFFSET 0
-#define STABLE_VFP_OFFSET 16
-#define CMD_ALLOW_OFFSET 28
-
-#define MAIN_HBP_OFFSET 0
-#define MAIN_HFP_OFFSET 16
-
-#define MAIN_HSA_OFFSET 0
-#define MAIN_VSA_OFFSET 22
-
-#define MAIN_STANDBY (1 << 31)
-#define MAIN_VRESOL_OFFSET 16
-#define MAIN_HRESOL_OFFSET 0
-
-#define SFR_FIFO_EMPTY (1 << 29)
-
-#define DSIM_PLL_EN_SHIFT (1 << 23)
-#define PLL_STABLE (1 << 31)
-
-#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
-#define DSIM_STOP_STATE_CLK (1 << 8)
-#define DSIM_TX_READY_HS_CLK (1 << 10)
-
-#endif
diff --git a/src/soc/samsung/exynos5250/mct.c b/src/soc/samsung/exynos5250/mct.c
deleted file mode 100644
index bbb90e4..0000000
--- a/src/soc/samsung/exynos5250/mct.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include "clk.h"
-
-uint64_t mct_raw_value(void)
-{
- uint64_t upper = readl(&exynos_mct->g_cnt_u);
- uint64_t lower = readl(&exynos_mct->g_cnt_l);
-
- return (upper << 32) | lower;
-}
-
-void mct_start(void)
-{
- writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
- &exynos_mct->g_tcon);
-}
diff --git a/src/soc/samsung/exynos5250/monotonic_timer.c b/src/soc/samsung/exynos5250/monotonic_timer.c
deleted file mode 100644
index 89ac416..0000000
--- a/src/soc/samsung/exynos5250/monotonic_timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <timer.h>
-
-#include "clk.h"
-
-static const uint32_t clocks_per_usec = MCT_HZ/1000000;
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- /* We don't have to call mct_start() here
- * because it was already called in the bootblock
- */
-
- mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec);
-}
diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c
deleted file mode 100644
index 7d94712..0000000
--- a/src/soc/samsung/exynos5250/power.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Power setup code for EXYNOS5 */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <halt.h>
-#include "dmc.h"
-#include "power.h"
-#include "setup.h"
-
-/* Set the PS-Hold drive value */
-static void ps_hold_setup(void)
-{
- /* Set PS-Hold high */
- setbits_le32(&exynos_power->ps_hold_ctrl,
- POWER_PS_HOLD_CONTROL_DATA_HIGH);
-}
-
-void power_reset(void)
-{
- /* Clear inform1 so there's no change we think we've got a wake reset */
- exynos_power->inform1 = 0;
-
- setbits_le32(&exynos_power->sw_reset, 1);
-}
-
-/* This function never returns */
-void power_shutdown(void)
-{
- clrbits_le32(&exynos_power->ps_hold_ctrl,
- POWER_PS_HOLD_CONTROL_DATA_HIGH);
-
- halt();
-}
-
-void power_enable_dp_phy(void)
-{
- setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
-}
-
-void power_enable_hw_thermal_trip(void)
-{
- /* Enable HW thermal trip */
- setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
-}
-
-uint32_t power_read_reset_status(void)
-{
- return exynos_power->inform1;
-}
-
-void power_exit_wakeup(void)
-{
- typedef void (*resume_func)(void);
-
- ((resume_func)exynos_power->inform0)();
-}
-
-int power_init(void)
-{
- ps_hold_setup();
- return 0;
-}
-
-void power_enable_xclkout(void)
-{
- /* use xxti for xclk out */
- clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
- PMU_DEBUG_XXTI);
-}
-
-void power_release_uart_retention(void)
-{
- writel(1 << 28, &exynos_power->padret_uart_opt);
-}
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index c02cdf7..bc2883d 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -21,11 +21,10 @@
#include <console/uart.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
-#include "uart.h"
#include "clk.h"
#include "cpu.h"
#include "periph.h"
-#include "uart.h"
+#include "../exynos/uart.h"
#define RX_FIFO_COUNT_MASK 0xff
#define RX_FIFO_FULL_MASK (1 << 8)
diff --git a/src/soc/samsung/exynos5250/uart.h b/src/soc/samsung/exynos5250/uart.h
deleted file mode 100644
index e2514d7..0000000
--- a/src/soc/samsung/exynos5250/uart.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012 Google Inc.
- * Copyright (C) 2009 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5250_UART_H
-#define CPU_SAMSUNG_EXYNOS5250_UART_H
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- unsigned char res3[0xffd0];
-};
-check_member(s5p_uart, ubrdiv, 0x28);
-
-#endif
diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c
deleted file mode 100644
index 76da1dd..0000000
--- a/src/soc/samsung/exynos5250/usb.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <delay.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include "gpio.h"
-#include "power.h"
-#include "sysreg.h"
-#include "usb.h"
-
-static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
-{
- setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */
- setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
- setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
-}
-
-void reset_usb_drd_dwc3()
-{
- printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD\n");
- reset_dwc3(exynos_usb_drd_dwc3);
-}
-
-static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
-{
- if (!(dwc3->ctl & 0x1 << 11) ||
- !(dwc3->usb3pipectl & 0x1 << 31) ||
- !(dwc3->usb2phycfg & 0x1 << 31)) {
- printk(BIOS_ERR, "DWC3 at %p not in reset (you need to call "
- "reset_usb_drd_dwc3() first)!\n", dwc3);
- }
-
- /* Set relevant registers to default values (clearing all reset bits) */
-
- writel(0x1 << 24 | /* activate PHY low power states */
- 0x4 << 19 | /* low power delay value */
- 0x1 << 18 | /* activate PHY low power delay */
- 0x1 << 17 | /* enable SuperSpeed PHY suspend */
- 0x1 << 1 | /* default Tx deemphasis value */
- 0, &dwc3->usb3pipectl);
-
- /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
- writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */
- 0x1 << 8 | /* enable PHY sleep in L1 */
- 0x1 << 6 | /* enable PHY suspend */
- 0, &dwc3->usb2phycfg);
-
- writel(0x5dc << 19 | /* suspend clock scale for 24MHz */
- 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */
- 0x1 << 12 | /* port capability HOST */
- 0, &dwc3->ctl);
-}
-
-void setup_usb_drd_dwc3()
-{
- setup_dwc3(exynos_usb_drd_dwc3);
- printk(BIOS_DEBUG, "DWC3 setup for USB DRD finished\n");
-}
-
-static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
-{
- /* Set all PHY registers to default values */
-
- /* XHCI Version 1.0, Frame Length adjustment 30 MHz */
- setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
-
- /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
- writel(1 << 6, &phy->utmi);
-
- writel(0x88 << 23 | /* spread spectrum refclk selector */
- 0x1 << 20 | /* enable spread spectrum */
- 0x1 << 19 | /* enable prescaler refclk */
- 0x68 << 11 | /* multiplier for 24MHz refclk */
- 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */
- 0x1 << 4 | /* power supply in normal operating mode */
- 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/
- 0x1 << 1 | /* force port reset */
- 0x1 << 0 | /* normal operating mode */
- 0, &phy->clkrst);
-
- writel(0x9 << 26 | /* LOS level */
- 0x3 << 22 | /* TX VREF tune */
- 0x1 << 20 | /* TX rise tune */
- 0x1 << 18 | /* TX res tune */
- 0x3 << 13 | /* TX HS X Vtune */
- 0x3 << 9 | /* TX FS/LS tune */
- 0x3 << 6 | /* SQRX tune */
- 0x4 << 3 | /* OTG tune */
- 0x4 << 0 | /* comp disc tune */
- 0, &phy->param0);
-
- writel(0x7f << 19 | /* reserved */
- 0x7f << 12 | /* Tx launch amplitude */
- 0x20 << 6 | /* Tx deemphasis 6dB */
- 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */
- 0, &phy->param1);
-
- /* disable all test features */
- writel(0, &phy->test);
-
- /* UTMI clock select? ("must be 0x1") */
- writel(0x1 << 2, &phy->utmiclksel);
-
- /* Samsung magic, undocumented (from U-Boot) */
- writel(0x0, &phy->resume);
-
- udelay(10);
- clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
-}
-
-void setup_usb_drd_phy()
-{
- printk(BIOS_DEBUG, "Powering up USB DRD PHY\n");
- setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN);
- setup_drd_phy(exynos_usb_drd_phy);
-}
-
-void setup_usb_host_phy(int hsic_gpio)
-{
- unsigned int hostphy_ctrl0;
-
- setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
- setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
-
- printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
- hsic_gpio ? "with" : "without");
-
- hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
- hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
- HOST_CTRL0_COMMONON_N |
- /* HOST Phy setting */
- HOST_CTRL0_PHYSWRST |
- HOST_CTRL0_PHYSWRSTALL |
- HOST_CTRL0_SIDDQ |
- HOST_CTRL0_FORCESUSPEND |
- HOST_CTRL0_FORCESLEEP);
- hostphy_ctrl0 |= (/* Setting up the ref freq */
- CLK_24MHZ << 16 |
- /* HOST Phy setting */
- HOST_CTRL0_LINKSWRST |
- HOST_CTRL0_UTMISWRST);
- writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
- udelay(10);
- clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
- HOST_CTRL0_LINKSWRST |
- HOST_CTRL0_UTMISWRST);
- udelay(20);
-
- /* EHCI Ctrl setting */
- setbits_le32(&exynos_usb_host_phy->ehcictrl,
- EHCICTRL_ENAINCRXALIGN |
- EHCICTRL_ENAINCR4 |
- EHCICTRL_ENAINCR8 |
- EHCICTRL_ENAINCR16);
-
- /* HSIC USB Hub initialization. */
- if (hsic_gpio) {
- gpio_direction_output(hsic_gpio, 0);
- udelay(100);
- gpio_direction_output(hsic_gpio, 1);
- udelay(5000);
-
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_SIDDQ |
- HOST_CTRL0_FORCESLEEP |
- HOST_CTRL0_FORCESUSPEND);
- setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
- udelay(10);
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
- }
-
- /* At this point we need to wait for 50ms before talking to
- * the USB controller (PHY clock and power setup time)
- * By the time we are actually in the payload, these 50ms
- * will have passed.
- */
-}
diff --git a/src/soc/samsung/exynos5250/usb.h b/src/soc/samsung/exynos5250/usb.h
deleted file mode 100644
index 20a2257..0000000
--- a/src/soc/samsung/exynos5250/usb.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5250_USB_H
-#define CPU_SAMSUNG_EXYNOS5250_USB_H
-
-#include "cpu.h"
-
-#define CLK_24MHZ 5
-
-#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
-#define HOST_CTRL0_COMMONON_N (1 << 9)
-#define HOST_CTRL0_SIDDQ (1 << 6)
-#define HOST_CTRL0_FORCESLEEP (1 << 5)
-#define HOST_CTRL0_FORCESUSPEND (1 << 4)
-#define HOST_CTRL0_WORDINTERFACE (1 << 3)
-#define HOST_CTRL0_UTMISWRST (1 << 2)
-#define HOST_CTRL0_LINKSWRST (1 << 1)
-#define HOST_CTRL0_PHYSWRST (1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK (7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN (1 << 29)
-#define EHCICTRL_ENAINCR4 (1 << 28)
-#define EHCICTRL_ENAINCR8 (1 << 27)
-#define EHCICTRL_ENAINCR16 (1 << 26)
-
-/* Register map for PHY control */
-struct exynos5_usb_host_phy {
- uint32_t usbphyctrl0;
- uint32_t usbphytune0;
- uint8_t reserved1[8];
- uint32_t hsicphyctrl1;
- uint32_t hsicphytune1;
- uint8_t reserved2[8];
- uint32_t hsicphyctrl2;
- uint32_t hsicphytune2;
- uint8_t reserved3[8];
- uint32_t ehcictrl;
- uint32_t ohcictrl;
- uint32_t usbotgsys;
- uint8_t reserved4[4];
- uint32_t usbotgtune;
-};
-check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
-
-static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
- (void *)EXYNOS5_USB_HOST_PHY_BASE;
-
-struct exynos5_usb_drd_phy {
- uint8_t reserved1[4];
- uint32_t linksystem;
- uint32_t utmi;
- uint32_t pipe;
- uint32_t clkrst;
- uint32_t reg0;
- uint32_t reg1;
- uint32_t param0;
- uint32_t param1;
- uint32_t term;
- uint32_t test;
- uint32_t adp;
- uint32_t utmiclksel;
- uint32_t resume;
- uint8_t reserved2[8];
- uint32_t linkhcbelt;
- uint32_t linkport;
-};
-check_member(exynos5_usb_drd_phy, linkport, 0x44);
-
-static struct exynos5_usb_drd_phy * const exynos_usb_drd_phy =
- (void *)EXYNOS5_USB_DRD_PHY_BASE;
-
-struct exynos5_usb_drd_dwc3 {
- uint32_t sbuscfg0;
- uint32_t sbuscfg1;
- uint32_t txthrcfg;
- uint32_t rxthrcfg;
- uint32_t ctl;
- uint32_t evten;
- uint32_t sts;
- uint8_t reserved0[4];
- uint32_t snpsid;
- uint32_t gpio;
- uint32_t uid;
- uint32_t uctl;
- uint64_t buserraddr;
- uint64_t prtbimap;
- uint8_t reserved1[32];
- uint32_t dbgfifospace;
- uint32_t dbgltssm;
- uint32_t dbglnmcc;
- uint32_t dbgbmu;
- uint32_t dbglspmux;
- uint32_t dbglsp;
- uint32_t dbgepinfo0;
- uint32_t dbgepinfo1;
- uint64_t prtbimap_hs;
- uint64_t prtbimap_fs;
- uint8_t reserved2[112];
- uint32_t usb2phycfg;
- uint8_t reserved3[60];
- uint32_t usb2i2cctl;
- uint8_t reserved4[60];
- uint32_t usb2phyacc;
- uint8_t reserved5[60];
- uint32_t usb3pipectl;
- uint8_t reserved6[60];
-};
-check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
-
-static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd_dwc3 =
- (void *)EXYNOS5_USB_DRD_DWC3_BASE;
-
-/* Leave hsic_gpio at 0 to not enable HSIC. */
-void setup_usb_host_phy(int hsic_gpio);
-
-void setup_usb_drd_phy(void);
-
-/* Call reset_ before setup_, ensure at least 100ms pass in between. */
-void reset_usb_drd_dwc3(void);
-void setup_usb_drd_dwc3(void);
-
-#endif
diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig
index 904091e..abb0f30 100644
--- a/src/soc/samsung/exynos5420/Kconfig
+++ b/src/soc/samsung/exynos5420/Kconfig
@@ -2,6 +2,7 @@ config CPU_SAMSUNG_EXYNOS5420
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
+ select CPU_SAMSUNG_EXYNOS
select CPU_HAS_BOOTBLOCK_INIT
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index ac22620..f70434b 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -1,10 +1,9 @@
bootblock-y += spi.c alternate_cbfs.c
bootblock-y += bootblock.c
-bootblock-y += pinmux.c mct.c power.c
+bootblock-y += pinmux.c
# Clock is required for UART
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c
-bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c
ifeq ($(CONFIG_DRIVERS_UART),y)
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
endif
@@ -19,34 +18,27 @@ romstage-y += clock_init.c
romstage-y += pinmux.c # required by s3c24x0_i2c and uart.
romstage-y += dmc_common.c
romstage-y += dmc_init_ddr3.c
-romstage-y += power.c
-romstage-y += mct.c
-romstage-y += monotonic_timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += wakeup.c
romstage-y += gpio.c
romstage-y += timer.c
+romstage-y += trustzone.c
romstage-y += i2c.c
#romstage-y += wdt.c
-romstage-y += cbmem.c
-romstage-y += trustzone.c
ramstage-y += spi.c alternate_cbfs.c
ramstage-y += clock.c
ramstage-y += clock_init.c
ramstage-y += pinmux.c
-ramstage-y += power.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
ramstage-y += cpu.c
ramstage-y += tmu.c
-ramstage-y += mct.c
-ramstage-y += monotonic_timer.c
ramstage-y += timer.c
ramstage-y += gpio.c
ramstage-y += i2c.c
ramstage-y += dp.c dp_lowlevel.c fimd.c
-ramstage-y += usb.c
-ramstage-y += cbmem.c
+
+CPPFLAGS_common += -Isrc/soc/samsung/exynos/
$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
cp $< $@
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.h b/src/soc/samsung/exynos5420/alternate_cbfs.h
deleted file mode 100644
index af7751d..0000000
--- a/src/soc/samsung/exynos5420/alternate_cbfs.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
-#define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
-
-/* These are pointers to function pointers. Double indirection! */
-static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
-static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
-static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
-static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
-static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
-
-#define SECONDARY_BASE_BOOT_USB 0xfeed0002
-static u32 * const iram_secondary_base = (u32 *)0x02020018;
-
-/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
-#define OM_STAT_SDMMC 0x4
-#define OM_STAT_EMMC 0x8
-#define OM_STAT_SPI 0x14
-#define OM_STAT_MASK 0x7f
-
-#if defined(__BOOT_BLOCK__)
- /* A small space in IRAM to hold the romstage-only image */
- static void * const alternate_cbfs_buffer =
- (void *)CONFIG_CBFS_CACHE_ADDRESS;
- static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
-#else
- /* Just put this anywhere in RAM that's far enough from anything else */
- /* TODO: Find a better way to "reserve" this region? */
- static void * const alternate_cbfs_buffer = (void *)0x77400000;
- static size_t const alternate_cbfs_size = 0xc00000;
-#endif
-
-#endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */
diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c
deleted file mode 100644
index 4650320..0000000
--- a/src/soc/samsung/exynos5420/cbmem.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stddef.h>
-#include <cbmem.h>
-#include "cpu.h"
-
-void *cbmem_top(void)
-{
- return (void *)(get_fb_base_kb() * KiB);
-}
diff --git a/src/soc/samsung/exynos5420/dsim.h b/src/soc/samsung/exynos5420/dsim.h
deleted file mode 100644
index 9ad55d7..0000000
--- a/src/soc/samsung/exynos5420/dsim.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Register map for Exynos5 MIPI-DSIM */
-
-#ifndef CPU_SAMSUNG_EXYNOS5420_DSIM_H
-#define CPU_SAMSUNG_EXYNOS5420_DSIM_H
-
-/* DSIM register map */
-struct exynos5_dsim {
- unsigned int status;
- unsigned int swrst;
- unsigned int clkctrl;
- unsigned int timeout;
- unsigned int config;
- unsigned int escmode;
- unsigned int mdresol;
- unsigned int mvporch;
- unsigned int mhporch;
- unsigned int msync;
- unsigned int sdresol;
- unsigned int intsrc;
- unsigned int intmsk;
- unsigned int pkthdr;
- unsigned int payload;
- unsigned int rxfifo;
- unsigned int res1;
- unsigned int fifoctrl;
- unsigned int res2;
- unsigned int pllctrl;
- unsigned int plltmr;
- unsigned int phyacchr;
- unsigned int phyacchr1;
-};
-check_member(exynos5_dsim, phyacchr1, 0x54);
-
-#define ENABLE 1
-#define DISABLE 0
-
-#define DSIM_SWRST (1 << 0)
-#define NUM_OF_DAT_LANE_IS_FOUR (3 << 5)
-#define DATA_LANE_0_EN (1 << 0)
-#define DATA_LANE_1_EN (1 << 1)
-#define DATA_LANE_2_EN (1 << 2)
-#define DATA_LANE_3_EN (1 << 3)
-#define CLK_LANE_EN (1 << 4)
-#define ENABLE_ALL_DATA_LANE DATA_LANE_0_EN | \
- DATA_LANE_1_EN | \
- DATA_LANE_2_EN | \
- DATA_LANE_3_EN
-#define MAIN_PIX_FORMAT_OFFSET 12
-#define RGB_565_16_BIT 0x4
-#define VIDEO_MODE (1 << 25)
-#define BURST_MODE (1 << 26)
-
-
-#define DSIM_PHYACCHR_AFC_EN (1 << 14)
-#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5
-
-#define DSIM_PLLCTRL_PMS_OFFSET 1
-#define DSIM_FREQ_BAND_OFFSET 24
-
-#define LANE_ESC_CLK_EN_ALL (0x1f << 19)
-#define BYTE_CLK_EN (1 << 24)
-#define DSIM_ESC_CLK_EN (1 << 28)
-#define TXREQUEST_HS_CLK_ON (1 << 31)
-
-#define LP_MODE_ENABLE (1 << 7)
-#define STOP_STATE_CNT_OFFSET 21
-
-#define MAIN_VBP_OFFSET 0
-#define STABLE_VFP_OFFSET 16
-#define CMD_ALLOW_OFFSET 28
-
-#define MAIN_HBP_OFFSET 0
-#define MAIN_HFP_OFFSET 16
-
-#define MAIN_HSA_OFFSET 0
-#define MAIN_VSA_OFFSET 22
-
-#define MAIN_STANDBY (1 << 31)
-#define MAIN_VRESOL_OFFSET 16
-#define MAIN_HRESOL_OFFSET 0
-
-#define SFR_FIFO_EMPTY (1 << 29)
-
-#define DSIM_PLL_EN_SHIFT (1 << 23)
-#define PLL_STABLE (1 << 31)
-
-#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
-#define DSIM_STOP_STATE_CLK (1 << 8)
-#define DSIM_TX_READY_HS_CLK (1 << 10)
-
-#endif
diff --git a/src/soc/samsung/exynos5420/mct.c b/src/soc/samsung/exynos5420/mct.c
deleted file mode 100644
index bbb90e4..0000000
--- a/src/soc/samsung/exynos5420/mct.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include "clk.h"
-
-uint64_t mct_raw_value(void)
-{
- uint64_t upper = readl(&exynos_mct->g_cnt_u);
- uint64_t lower = readl(&exynos_mct->g_cnt_l);
-
- return (upper << 32) | lower;
-}
-
-void mct_start(void)
-{
- writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
- &exynos_mct->g_tcon);
-}
diff --git a/src/soc/samsung/exynos5420/monotonic_timer.c b/src/soc/samsung/exynos5420/monotonic_timer.c
deleted file mode 100644
index 89ac416..0000000
--- a/src/soc/samsung/exynos5420/monotonic_timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <timer.h>
-
-#include "clk.h"
-
-static const uint32_t clocks_per_usec = MCT_HZ/1000000;
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- /* We don't have to call mct_start() here
- * because it was already called in the bootblock
- */
-
- mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec);
-}
diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c
deleted file mode 100644
index 7d94712..0000000
--- a/src/soc/samsung/exynos5420/power.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Power setup code for EXYNOS5 */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <halt.h>
-#include "dmc.h"
-#include "power.h"
-#include "setup.h"
-
-/* Set the PS-Hold drive value */
-static void ps_hold_setup(void)
-{
- /* Set PS-Hold high */
- setbits_le32(&exynos_power->ps_hold_ctrl,
- POWER_PS_HOLD_CONTROL_DATA_HIGH);
-}
-
-void power_reset(void)
-{
- /* Clear inform1 so there's no change we think we've got a wake reset */
- exynos_power->inform1 = 0;
-
- setbits_le32(&exynos_power->sw_reset, 1);
-}
-
-/* This function never returns */
-void power_shutdown(void)
-{
- clrbits_le32(&exynos_power->ps_hold_ctrl,
- POWER_PS_HOLD_CONTROL_DATA_HIGH);
-
- halt();
-}
-
-void power_enable_dp_phy(void)
-{
- setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
-}
-
-void power_enable_hw_thermal_trip(void)
-{
- /* Enable HW thermal trip */
- setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
-}
-
-uint32_t power_read_reset_status(void)
-{
- return exynos_power->inform1;
-}
-
-void power_exit_wakeup(void)
-{
- typedef void (*resume_func)(void);
-
- ((resume_func)exynos_power->inform0)();
-}
-
-int power_init(void)
-{
- ps_hold_setup();
- return 0;
-}
-
-void power_enable_xclkout(void)
-{
- /* use xxti for xclk out */
- clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
- PMU_DEBUG_XXTI);
-}
-
-void power_release_uart_retention(void)
-{
- writel(1 << 28, &exynos_power->padret_uart_opt);
-}
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index 4d71155..496de4f 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -21,7 +21,6 @@
#include <console/uart.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
-#include "uart.h"
#include "clk.h"
#include "cpu.h"
#include "periph.h"
diff --git a/src/soc/samsung/exynos5420/uart.h b/src/soc/samsung/exynos5420/uart.h
deleted file mode 100644
index ed78f60..0000000
--- a/src/soc/samsung/exynos5420/uart.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2012 Google Inc.
- * Copyright (C) 2009 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5420_UART_H
-#define CPU_SAMSUNG_EXYNOS5420_UART_H
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- unsigned char res3[0xffd0];
-};
-check_member(s5p_uart, ubrdiv, 0x28);
-
-#endif
diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c
deleted file mode 100644
index 84a6f4c..0000000
--- a/src/soc/samsung/exynos5420/usb.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <delay.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include "gpio.h"
-#include "power.h"
-#include "sysreg.h"
-#include "usb.h"
-
-static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
-{
- setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */
- setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */
- setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */
-}
-
-void reset_usb_drd0_dwc3()
-{
- printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD0\n");
- reset_dwc3(exynos_usb_drd0_dwc3);
-}
-
-void reset_usb_drd1_dwc3()
-{
- printk(BIOS_DEBUG, "Starting DWC3 reset for USB DRD1\n");
- reset_dwc3(exynos_usb_drd1_dwc3);
-}
-
-static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
-{
- if (!(dwc3->ctl & 0x1 << 11) ||
- !(dwc3->usb3pipectl & 0x1 << 31) ||
- !(dwc3->usb2phycfg & 0x1 << 31)) {
- printk(BIOS_ERR, "DWC3 at %p not in reset (you need to call "
- "reset_usb_drdX_dwc3() first)!\n", dwc3);
- }
-
- /* Set relevant registers to default values (clearing all reset bits) */
-
- writel(0x1 << 24 | /* activate PHY low power states */
- 0x4 << 19 | /* low power delay value */
- 0x1 << 18 | /* activate PHY low power delay */
- 0x1 << 17 | /* enable SuperSpeed PHY suspend */
- 0x1 << 1 | /* default Tx deemphasis value */
- 0, &dwc3->usb3pipectl);
-
- /* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
- writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */
- 0x1 << 8 | /* enable PHY sleep in L1 */
- 0x1 << 6 | /* enable PHY suspend */
- 0, &dwc3->usb2phycfg);
-
- writel(0x5dc << 19 | /* suspend clock scale for 24MHz */
- 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */
- 0x1 << 12 | /* port capability HOST */
- 0, &dwc3->ctl);
-}
-
-void setup_usb_drd0_dwc3()
-{
- setup_dwc3(exynos_usb_drd0_dwc3);
- printk(BIOS_DEBUG, "DWC3 setup for USB DRD0 finished\n");
-}
-
-void setup_usb_drd1_dwc3()
-{
- setup_dwc3(exynos_usb_drd1_dwc3);
- printk(BIOS_DEBUG, "DWC3 setup for USB DRD1 finished\n");
-}
-
-static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
-{
- /* Set all PHY registers to default values */
-
- /* XHCI Version 1.0, Frame Length adjustment 30 MHz */
- setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
-
- /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
- writel(1 << 6, &phy->utmi);
-
- writel(0x88 << 23 | /* spread spectrum refclk selector */
- 0x1 << 20 | /* enable spread spectrum */
- 0x1 << 19 | /* enable prescaler refclk */
- 0x68 << 11 | /* multiplier for 24MHz refclk */
- 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */
- 0x1 << 4 | /* power supply in normal operating mode */
- 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/
- 0x1 << 1 | /* force port reset */
- 0x1 << 0 | /* normal operating mode */
- 0, &phy->clkrst);
-
- writel(0x9 << 26 | /* LOS level */
- 0x3 << 22 | /* TX VREF tune */
- 0x1 << 20 | /* TX rise tune */
- 0x1 << 18 | /* TX res tune */
- 0x3 << 13 | /* TX HS X Vtune */
- 0x3 << 9 | /* TX FS/LS tune */
- 0x3 << 6 | /* SQRX tune */
- 0x4 << 3 | /* OTG tune */
- 0x4 << 0 | /* comp disc tune */
- 0, &phy->param0);
-
- writel(0x7f << 19 | /* reserved */
- 0x7f << 12 | /* Tx launch amplitude */
- 0x20 << 6 | /* Tx deemphasis 6dB */
- 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */
- 0, &phy->param1);
-
- /* disable all test features */
- writel(0, &phy->test);
-
- /* UTMI clock select? ("must be 0x1") */
- writel(0x1 << 2, &phy->utmiclksel);
-
- /* Samsung magic, undocumented (from U-Boot) */
- writel(0x0, &phy->resume);
-
- udelay(10);
- clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
-}
-
-void setup_usb_drd0_phy()
-{
- printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n");
- setbits_le32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN);
- setup_drd_phy(exynos_usb_drd0_phy);
-}
-
-void setup_usb_drd1_phy()
-{
- printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n");
- setbits_le32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN);
- setup_drd_phy(exynos_usb_drd1_phy);
-}
-
-void setup_usb_host_phy(int hsic_gpio)
-{
- unsigned int hostphy_ctrl0;
-
- setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
- setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN);
-
- printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
- hsic_gpio ? "with" : "without");
-
- hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
- hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
- HOST_CTRL0_COMMONON_N |
- /* HOST Phy setting */
- HOST_CTRL0_PHYSWRST |
- HOST_CTRL0_PHYSWRSTALL |
- HOST_CTRL0_SIDDQ |
- HOST_CTRL0_FORCESUSPEND |
- HOST_CTRL0_FORCESLEEP);
- hostphy_ctrl0 |= (/* Setting up the ref freq */
- CLK_24MHZ << 16 |
- /* HOST Phy setting */
- HOST_CTRL0_LINKSWRST |
- HOST_CTRL0_UTMISWRST);
- writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
- udelay(10);
- clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
- HOST_CTRL0_LINKSWRST |
- HOST_CTRL0_UTMISWRST);
- udelay(20);
-
- /* EHCI Ctrl setting */
- setbits_le32(&exynos_usb_host_phy->ehcictrl,
- EHCICTRL_ENAINCRXALIGN |
- EHCICTRL_ENAINCR4 |
- EHCICTRL_ENAINCR8 |
- EHCICTRL_ENAINCR16);
-
- /* HSIC USB Hub initialization. */
- if (hsic_gpio) {
- gpio_direction_output(hsic_gpio, 0);
- udelay(100);
- gpio_direction_output(hsic_gpio, 1);
- udelay(5000);
-
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_SIDDQ |
- HOST_CTRL0_FORCESLEEP |
- HOST_CTRL0_FORCESUSPEND);
- setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
- udelay(10);
- clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
- HOST_CTRL0_PHYSWRST);
- }
-
- /* At this point we need to wait for 50ms before talking to
- * the USB controller (PHY clock and power setup time)
- * By the time we are actually in the payload, these 50ms
- * will have passed.
- */
-}
diff --git a/src/soc/samsung/exynos5420/usb.h b/src/soc/samsung/exynos5420/usb.h
deleted file mode 100644
index 599b944..0000000
--- a/src/soc/samsung/exynos5420/usb.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Samsung Electronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef CPU_SAMSUNG_EXYNOS5420_USB_H
-#define CPU_SAMSUNG_EXYNOS5420_USB_H
-
-#include "cpu.h"
-
-#define CLK_24MHZ 5
-
-#define HOST_CTRL0_PHYSWRSTALL (1 << 31)
-#define HOST_CTRL0_COMMONON_N (1 << 9)
-#define HOST_CTRL0_SIDDQ (1 << 6)
-#define HOST_CTRL0_FORCESLEEP (1 << 5)
-#define HOST_CTRL0_FORCESUSPEND (1 << 4)
-#define HOST_CTRL0_WORDINTERFACE (1 << 3)
-#define HOST_CTRL0_UTMISWRST (1 << 2)
-#define HOST_CTRL0_LINKSWRST (1 << 1)
-#define HOST_CTRL0_PHYSWRST (1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK (7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN (1 << 29)
-#define EHCICTRL_ENAINCR4 (1 << 28)
-#define EHCICTRL_ENAINCR8 (1 << 27)
-#define EHCICTRL_ENAINCR16 (1 << 26)
-
-/* Register map for PHY control */
-struct exynos5_usb_host_phy {
- uint32_t usbphyctrl0;
- uint32_t usbphytune0;
- uint8_t reserved1[8];
- uint32_t hsicphyctrl1;
- uint32_t hsicphytune1;
- uint8_t reserved2[8];
- uint32_t hsicphyctrl2;
- uint32_t hsicphytune2;
- uint8_t reserved3[8];
- uint32_t ehcictrl;
- uint32_t ohcictrl;
- uint32_t usbotgsys;
- uint8_t reserved4[4];
- uint32_t usbotgtune;
-};
-check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
-
-static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
- (void *)EXYNOS5_USB_HOST_PHY_BASE;
-
-struct exynos5_usb_drd_phy {
- uint8_t reserved1[4];
- uint32_t linksystem;
- uint32_t utmi;
- uint32_t pipe;
- uint32_t clkrst;
- uint32_t reg0;
- uint32_t reg1;
- uint32_t param0;
- uint32_t param1;
- uint32_t term;
- uint32_t test;
- uint32_t adp;
- uint32_t utmiclksel;
- uint32_t resume;
- uint8_t reserved2[8];
- uint32_t linkhcbelt;
- uint32_t linkport;
-};
-check_member(exynos5_usb_drd_phy, linkport, 0x44);
-
-static struct exynos5_usb_drd_phy * const exynos_usb_drd0_phy =
- (void *)EXYNOS5420_USB_DRD0_PHY_BASE;
-static struct exynos5_usb_drd_phy * const exynos_usb_drd1_phy =
- (void *)EXYNOS5420_USB_DRD1_PHY_BASE;
-
-struct exynos5_usb_drd_dwc3 {
- uint32_t sbuscfg0;
- uint32_t sbuscfg1;
- uint32_t txthrcfg;
- uint32_t rxthrcfg;
- uint32_t ctl;
- uint32_t evten;
- uint32_t sts;
- uint8_t reserved0[4];
- uint32_t snpsid;
- uint32_t gpio;
- uint32_t uid;
- uint32_t uctl;
- uint64_t buserraddr;
- uint64_t prtbimap;
- uint8_t reserved1[32];
- uint32_t dbgfifospace;
- uint32_t dbgltssm;
- uint32_t dbglnmcc;
- uint32_t dbgbmu;
- uint32_t dbglspmux;
- uint32_t dbglsp;
- uint32_t dbgepinfo0;
- uint32_t dbgepinfo1;
- uint64_t prtbimap_hs;
- uint64_t prtbimap_fs;
- uint8_t reserved2[112];
- uint32_t usb2phycfg;
- uint8_t reserved3[60];
- uint32_t usb2i2cctl;
- uint8_t reserved4[60];
- uint32_t usb2phyacc;
- uint8_t reserved5[60];
- uint32_t usb3pipectl;
- uint8_t reserved6[60];
-};
-check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
-
-static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd0_dwc3 =
- (void *)EXYNOS5420_USB_DRD0_DWC3_BASE;
-static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd1_dwc3 =
- (void *)EXYNOS5420_USB_DRD1_DWC3_BASE;
-
-/* Leave hsic_gpio at 0 to not enable HSIC. */
-void setup_usb_host_phy(int hsic_gpio);
-
-void setup_usb_drd0_phy(void);
-void setup_usb_drd1_phy(void);
-
-/* Call reset_ before setup_, ensure at least 100ms pass in between. */
-void reset_usb_drd0_dwc3(void);
-void reset_usb_drd1_dwc3(void);
-void setup_usb_drd0_dwc3(void);
-void setup_usb_drd1_dwc3(void);
-
-#endif
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