[coreboot-gerrit] New patch to review for coreboot: 9656c1a tegra124: Active dc/sor register change immediately

[Marc Jones (marc.jones@se-eng.com)]

Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7951

-gerrit

commit 9656c1a22c09e60ad194fa222a8420c5bb4908ec
Author: Vince Hsu <vinceh at nvidia.com>
Date:   Fri May 16 18:07:53 2014 +0800

    tegra124: Active dc/sor register change immediately
    
    When doing DP attach, we need to make sure the register change to
    take effect immediately, otherwise it may fail to catch the attach
    timing.
    
    BRANCH=None
    BUG=chrome-os-partner:28128
    TEST=Display works and system boots up on Nyan and Big
    
    Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d
    Original-Signed-off-by: Vince Hsu <vinceh at nvidia.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/200414
    Original-Reviewed-by: Hung-Te Lin <hungte at chromium.org>
    Original-Reviewed-by: Jimmy Zhang <jimmzhang at nvidia.com>
    Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02)
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
    
    Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a
---
 src/soc/nvidia/tegra124/sor.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index 0e96764..2c059bf 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -762,9 +762,11 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
 	tegra_dc_sor_super_update(sor);
 
 	/* Enable dc */
+	reg_val = READL(&disp_ctrl->cmd.state_access);
+	WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 	WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
 	WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
-	WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+	WRITEL(reg_val, &disp_ctrl->cmd.state_access);
 
 	if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
 			NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,