[coreboot-gerrit] New patch to review for coreboot: 9cde084 southbridge/intel/*/lpc.c: Use 'BIOS_CNTL' define over 0xdc magic
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Tue Dec 30 14:20:45 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7989
-gerrit
commit 9cde0840ab57caddaa44e67892952fbe09f77eec
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Wed Dec 31 00:17:56 2014 +1100
southbridge/intel/*/lpc.c: Use 'BIOS_CNTL' define over 0xdc magic
We define BIOS_CNTL - BIOS Control Register (LPC I/F-D31:F0) in
headers, so lets make use of it in code over the raw magic value.
Change-Id: If9b94a0f20c06fa4a8f156c11a794a61767ec7cd
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/soc/intel/broadwell/broadwell/lpc.h | 2 +-
src/southbridge/intel/bd82x6x/lpc.c | 16 ++++++++--------
src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++--------
src/southbridge/intel/fsp_rangeley/lpc.c | 4 ++--
src/southbridge/intel/i82801gx/lpc.c | 12 ++++++------
src/southbridge/intel/i82801ix/lpc.c | 12 ++++++------
src/southbridge/intel/ibexpeak/lpc.c | 16 ++++++++--------
7 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/src/soc/intel/broadwell/broadwell/lpc.h b/src/soc/intel/broadwell/broadwell/lpc.h
index 180e527..8dd7f10 100644
--- a/src/soc/intel/broadwell/broadwell/lpc.h
+++ b/src/soc/intel/broadwell/broadwell/lpc.h
@@ -34,7 +34,7 @@
#define SCIS_IRQ22 6
#define SCIS_IRQ23 7
#define GPIOBASE 0x48
-#define BIOS_CNTL 0xdc
+#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
#define GPIO_EN (1 << 4)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 11b765a..e5b5595 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -454,15 +454,15 @@ static void pch_lock_smm(struct device *dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL);
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
@@ -470,9 +470,9 @@ static void pch_lock_smm(struct device *dev)
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
@@ -485,9 +485,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void pch_fixups(struct device *dev)
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index f9961f9..2b7ae84 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -432,15 +432,15 @@ static void pch_lock_smm(struct device *dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
@@ -448,9 +448,9 @@ static void pch_lock_smm(struct device *dev)
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
@@ -463,9 +463,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void pch_fixups(struct device *dev)
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 9644067..7b79dd3 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -304,9 +304,9 @@ static void soc_disable_smm_only_flashing(struct device *dev)
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void lpc_init(struct device *dev)
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 6b9d11e..b4f7066 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -356,15 +356,15 @@ static void i82801gx_lock_smm(struct device *dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
@@ -372,9 +372,9 @@ static void i82801gx_lock_smm(struct device *dev)
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 6038eff..815cab1 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -401,15 +401,15 @@ static void i82801ix_lock_smm(struct device *dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
@@ -417,9 +417,9 @@ static void i82801ix_lock_smm(struct device *dev)
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 2124711..0b87bd2 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -460,15 +460,15 @@ static void pch_lock_smm(struct device *dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
reg8 |= (1 << 1); /* set BLE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
printk(BIOS_DEBUG, "ok.\n");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
@@ -476,9 +476,9 @@ static void pch_lock_smm(struct device *dev)
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
@@ -491,9 +491,9 @@ static void pch_disable_smm_only_flashing(struct device *dev)
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
- reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
+ reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
- pci_write_config8(dev, 0xdc, reg8);
+ pci_write_config8(dev, BIOS_CNTL, reg8);
}
static void pch_fixups(struct device *dev)
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